• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 31 subscribers
  • Views 590 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

The definition of STC Test Coverage

Nomo
Guru 16800 points


Hi,

In page 338 (8.3) of TRM (spnu499), "Table 8-1. STC Test Coverage and Duration" is described.
What STC Test Coverage mean?
I want to know the numerator and the denominator for the coverage.

Also, could you teach me the detected faults by STC Test?
For example, in case of March13N, Address decoder faults, Stuck-At faults, Coupled faults and so on are detected, which is described in p.318 ("7.4 Memory Test Algorithms on the On-chip ROM").
I need the same information for LBIST.

Thanks

Nomoto

  • 0
    TI__Genius 9015 points

    Hello Nomoto,

    I have forwarded your question to the expert on this.  They will be responding soon.

  • 0 in reply to John Hall
    TI__Intellectual 1480 points

    Nemoto,

    The coverage nos shown in the TRM are traditional stuck-At Fault test coverage numbers generated by automatic test pattern tools.This  for pure digital logic which is the case for the CPU. Let me know if you need more information.

    Hercules forum support

     

  • 0 in reply to Hari Pendurty
    TI__Intellectual 1480 points

     

    •The definition of Test Coverage:

                 Test Coverage = Detected Faults / Detectable Faults 

                                                         DT + (PT x PT_Credit)

                                          =   ----------------------------------------- x 100

                                                            All Faults – UD

    •DT refers to Detected Faults which are further classified as below
        –DS : Detected by simulation.  Determined by generating patterns.
        –DI : Detected by implication. Determined by shifting the scan chains.
     
    •PT refers to Possibly Detected faults these  Faults for which the difference b/w the good machine and faulty machine results in simulated output of X rather than 1 or 0.
     PT_credit refers the credit we give to possibly detected faults in our case we give a credit of zero the most pessimistic scenario.
     
    •UD refers to undetectable faults : Faults cannot be detected by any means. Like Unused f  ,Tied  ,Blocked  and Redundant faults
    .
    Hercules forum support