TG Interrupt Structure

Nomo

Hi,

In page 1264 of TRM (spnu499), "Figure 25-23 TG Interrupt Structure" is described.
In this figure, I found that Vector (register?) is described, but what is this?
I can't understand what register corresponding to "Vector" and the meaning of "X + 1".
Please teach me.

Thanks

Nomoto

over 13 years ago

0 John Hall over 13 years ago

TI__Genius 9015 points

Hello Nomoto,

I have forwarded your question to the expert on this. They will be responding soon.

0 Jean-Marc Mifsud over 13 years ago in reply to John Hall

TI__Mastermind 22375 points

Nomoto,

The MIBSPI when used in multibuffer mode can support up to 16 Transfer Groups.

Each of the Transfer group, upon completion can generate an interrupt to the CPU.
For the CPU to know which transfer group is the source of the actual interrupt, the CPU will have to access the intvec0 or intvec1 (depending on which level is used).
The transfer group 0 to 15 will correspond to vector 1 to 16 respectively.

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TG Interrupt Structure