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SCI2 TX interrupt handling

Other Parts Discussed in Thread: HALCOGEN

Hello!

I am trying to establish UART communication. For this purpose SCI2 is selected, which is accessible on TMDX570LS20SUSB user's pins. At first this module was configured to transmit data without interrupts. Data transmission works normally in polling mode.

The next step is to use TX interrupt for data transmission. The first byte is sent from main (), but the next bytes should be transmitted from TX ISR. For this purpose TX INT (high level) for SCI2 is enabled from HalCoGen. VIM channel 13 is enabled too in HalCoGen as in the example HERCULES-SCIUART. I do not understand this because datasheet and HalCoGen show that  VIM channel 13 corresponds to LIN1 high. VIM channel is also configured to cause an IRQ. 

The CCS and HalcoGen projects are attached. 

2086.SCI.zip

I see that microcontroller sends only one first byte from main (); but TX interrupts never occur. So, TX interrupt does not operate correctly. Where is it necessary to handle interrupts? I found out from several examples that all interrupts should be handled in Notifications. You will see in the attached CCS project, that sciNotification is modified to send next byte . Is it correct? In this particular project only SCI2 TX interrupt should be enabled. But how is possible to handle both Rx and Tx interrupts?

I do not see that all SCI2 configuration, which was performed in HalCoGen, is done in the sciInit (); function. For example TX interrupt level is set to LOW and TX interrupt enable bit is not set. Am I right? And where is VIM configuration performed in the CCS accordingly to HalCoGen settings?

Does low level interrupt correspond to IRQ, but high level interrupt - to FIQ? Or not? FIQs will not be required for my application. Are the levels also denoted as low level = level 1 and high level = level 0? At the moment I am confused.

 

  • Hello Vitaly,

    I have forwarded your question to our HALCoGen team.  They will be responding soon.

  • Hi

    I see three main Questions

    1) How to use Interrupts in TMS570?

    - CortexR4 has IRQ and FIQ,
    - SCI Module ( Most of the other Module too ) has Level 0 / High and Level 1 / low which are configured using the Interrupt Level register inside Module. This does not have anything to do with IRQ and FIQ directly. Using VIM module you can map one of these interrupts either to IRQ or FIQ. So you can Enable Level 0 ( High) in the module and Map it to IRQ, FIQ need not be disturbed. HALCogen helps this configuration graphically using VIM Channel configration Tabs.
    - In the file you send I noticed you are configuring SCI2 but you have Enabled SCI1 interrupt in VIM channel. Please correct it.

    2) Why HALCoGen does not Enable TX_Interrupt on calling sci_Init?

    - This is done on purpose, If TX_Int is enabled in Init immediately an interrupt would be triggered. To avoid this we Enable TX_Interrupt only after a Data is written to the TD. This is done in the API  "sciSend(sciBASE_t *sci, uint32 length, uint8 * data)" In GUI if you have enabled TX_INT this API will automatically take care of functioning in interrupt mode. All you have to do is give the SCI innstance ( inyour case sciREG2), data length and the data pointer. After transmitting provided number of data the control is transfered to notification function.

    3) How to use notifications function?

    - Notification function is not the direct ISR routine. It is part of ISR in whcih the driver gives the handle to user with the "FLAG register details" so that user can do whatever he want to do with this.
    - In you case After the configured number of data is been transmitted control is transfereed to notification function with the Flag ( SCI_TX_INT).

    Notes:

    1) Try not to use TX interrupt and RX_Interrupt together.

    Regards
    Prathap

  • Hello Prathap,

    Thank you very much for answers.

    Now VIM channel 49 (IRQ) is enabled. I suppose it is LIN2 high. TX INT high level remained enabled for SCI2. Now "sciSend(sciBASE_t *sci, uint32 length, uint8 * data)" is used for data transmission. All bytes are transmitted successfully.

    The latest version of the example project is attached.

    3223.SCI.zip

    You tell that after transmitting provided number of data the control is transfered to notification function. But I see that NHET [0] LED does not turn ON after data transmission is completed. This task is performed in sciNotification. What could be the problem?

  • P.S.

    In my opinion polling mode is still used for data transmission because 'sciSend' returns  after transfer is complete. Waveform is attached. LED turns ON after 'sciSend' returns, when the last byte is places to SCITD register.

    In this case sciNotification is empty.

    void main(void)

    {

    /* USER CODE BEGIN (3) */

    hetREG-> DIR |= (1 << PIN_HET_0); // NHET [0] to output direction

    _enable_IRQ ();

    sciInit ();

    sciSend(sciREG2, 21, (unsigned char *) "Please press a key!\r\n");

    hetREG->DSET = (1 << PIN_HET_0);

    while (1)

    {}

    /* USER CODE END */

    }

    Should global interrupt enable bit set too or something like so?

  • Hello,

    Now interrupt based data transmission is working normally. The project is attached.

    3005.SCI.zip

    10 Byte data packet is sent in this example project. Now I wish to receive each sent byte. For this purpose RX INT high level is enabled in HalCoGen too. So, both TX INT high level and RX INT high level are enabled for SCI2. LIN2TX and LIN2RX pins are connected externally. But I see that RX interrupts are not generated as if RX INT is not enabled. What could be the problem? RX INT is enabled in the sciInit (). I suppose that both RX INT and TX INT may be used simultaneously. Code is modified not in the sciNotification () but directly in the ISR for sci2HighLevelInterrupt. Is it correctly?

    The final project will use RS485 interface for data transfer between different modules. So, RX and TX interrupts will not occur simultaneously. As I understand, RX and TX interrupts may appear in the same time. At fist RX interrupt will be processed, then TX interrupt in accordance to the priority of the interrupts. Am I right? 

    Best regards,

    Vitalij