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Need help for asm, nested interrupts, esm error on power on

Other Parts Discussed in Thread: RM48L952, HALCOGEN

Hello,

I'm still working on the irqDispatcher for nested interrupts and I did use the code published by Christian Hegert in this post: http://e2e.ti.com/support/microcontrollers/hercules/f/766/t/210653.aspx?pi239031349=3

I'm working with the target RM48L952. Some IRQ should be nested, one FIQ will run our fastest ISR.

I do encounter problems on power on.

If I start my target by power on, the nERROR pin is set (or if FIQ are enabled the esmGroup2 notification is called). Reason Group2 INTOFFH = 35, means CCMR4 compare.

If I soft reset my target afterwards, the error is not triggered.

I searched for the reason with help of a endless loop and found the line which does lead to this error. The error occurs at the first processing of a IRQ.

Found in irqDispatcher_a.asm

In there the system mode LR must be saved, which is done right after the stack alignment:

  PUSH     {R3, LR}       ; Put Stack adjustment and System Mode LR on Stack

For tests I did replace this command by 2 commands (I modified corresponding the POP cmd) :

  PUSH     {R3}       ; Put Stack adjustment on Stack

  PUSH     {LR}       ; Put System Mode LR on Stack

and then I did set once an endless loop before the PUSH LR and once after the PUSH LR

Test A:

  PUSH     {R3}       ; Put Stack adjustment on Stack

_stopLoop:

    B _stopLoop

  PUSH     {LR}       ; Put System Mode LR on Stack

Test B:

  PUSH     {R3}       ; Put Stack adjustment on Stack

  PUSH     {LR}       ; Put System Mode LR on Stack

_stopLoop:

    B _stopLoop

Results:

Test A no esm error

Test B esm error on power on (CCMR4 compare)

Any ideas?

Regards,

Roger

  • Hello Roger,

    I have forwarded your post to one of our experts.  They will be responding soon.

  • Hello John,

    Nice to meet you again :)

    Perhaps I found a hint right now.

    Our software is started "normally" with HALCoGen code. When landing in the main function we are in supervisor mode!

    I think this could be a problem, because at first IRQ the CPU switches to IRQ mode, in irqDispatcher we switch to system mode and do store the system Mode LR! But this is only correct if the system was in system / user mode before IRQ. It is correct if the ISR is interrupted by another IRQ (because running in system mode), but not if we interrupt the supervisor mode.

    Or am I wrong?

    Regards,

    Roger

  • Yeah! Found it!

    Adding (the red marked code) in the

    _coreInitRegisters_

     mov r0, lr

      ...; code by HALCoGEn

      ...; code by HALCoGEn

      cps #31
      mov lr, r0

    corrects it! Seems to be that it was the read access to a non initialized LR register which has caused the error!

    Ah, dear, HALCoGen Code....

    Please confirm that it would be nice, if HALCoGen would also init system mode registers.

    (lost a day now...)

    Regards,

    Roger

  • Hello Roger,

    I have forwarded your request to the HALCoGen team.

  • Hi Roger,

    Sorry for the Inconvenience. This issue has been reported to HALCoGen team and will be rolled out in the upcoming release.

    Regards
    Prathap