Hi,
We are going through some frustrating debugging time with the LM4F SSI module and it looks like we need your help!
The SSI2 module is used as a slave using Freescale SPI mode 2 and a bitrate of around 660 kHz. We need to process frames as fast as possible without polling the module with nonblocking functions. We think that the receive FIFO timeout interrupt should do the job.
The datasheet states that the timeout interrupt asserts after 32 bit clock periods. This is roughly equal to 48 us, and frames arrive periodically with an interval of 400 us. The problem is that it never triggers! Other interrupts, such as the receive FIFO half full work just fine.
Please see initialization code below. Kind Regards, Per
EDIT: For clarification, I can also say that by watching the status register when using the half full interrupt, it is possible to see that the SSI Receive FIFO Not Empty (RNE) bit indeed does go low and then high. Thus the initial condition for the timeout counter should be OK.
// Enable GPIO port H (PH7:PH4 are mapped to SSI2 peripheral)
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
// Enable SSI2 peripheral
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
// Configure the pin muxing for SSI2 functions on port H4, H5, H6 and H7.
GPIOPinConfigure(GPIO_PH4_SSI2CLK);
GPIOPinConfigure(GPIO_PH5_SSI2FSS);
GPIOPinConfigure(GPIO_PH6_SSI2RX);
GPIOPinConfigure(GPIO_PH7_SSI2TX);
// Configure the GPIO settings for the SSI pins. This function also gives
// control of these pins to the SSI hardware.
// The pins are assigned as follows:
// PH7 - SSI2Tx
// PH6 - SSI2Rx
// PH5 - SSI2Fss
// PH4 - SSI2CLK
GPIOPinTypeSSI(GPIO_PORTH_BASE,
GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4);
// Configure and enable the SSI2 port for Freescale SPI slave (PO=1, PH=0).
SSIConfigSetExpClk(SSI2_BASE, 50000000, SSI_FRF_MOTO_MODE_2,
SSI_MODE_SLAVE, 660000, 16);
// Enable the SSI2 module.
SSIEnable(SSI2_BASE);
// Enable RX timeout interrupt (asserted 32 bit clocks after a word is
// written to the empty RX FIFO
SSIIntEnable(SSI2_BASE, SSI_RXTO);
while (0 != ROM_SSIDataGetNonBlocking(SSI2_BASE, &rx_data))
{
// Read any residual frames
}
// Clear any pending interrupt
SSIIntClear(SSI2_BASE, SSI_RXTO);
// Gate SSI2 interrupts to mcu core
ROM_IntEnable(INT_SSI2);
