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TMS570LS20216 DMA request on SPI1_TX_EMPTY of standard SPI1 mode

So I setup the DMA channel 0 for 1x 16-bit element data transfer, whenever there is a SPI1 TX DMA request (enabled in the SPI1 module). However I don't see any data transfer after writing an initial 16-bit dummy write to the SPI1DAT1 register. Following is my code, please shed some light as on where should I look for debugging.

    DMAGCTRL        = 0x00000000;           // disable all DMA functions
    DMAHWCHENAS     = 0x00000001;           // channel 0:  MibSPI1 TX (Manchester test data stream)
    DMADREQASI0_bit.CH0ASI  = 0x01;         // channel 0:  request line #1 from MibSPI1 TX request

    DMAPAR0         = 0x70000000;           // channel 0:  use DMA Port B

    DMAGCTRL        = 0x00010000;           // enable all DMA functions


    DMACP0ISADDR    = (unsigned long) A708_TEST_MSGS;   // set of buffer address of loopback test bits array

    DMACP0IDADDR    = 0xFFF7F43C;           // MibSPI1DAT1 (fix destination) for data TX only
    DMACP0ITCOUNT   = 0x000C0001;           // frame transfer=12, element transfer=1
    DMACP0CHCTRL    = 0x00005009;           // RD/WR size: 16 bits, HW triggers one block transfer
                                            // RD mode: post increment, WR mode: constant
                                            // single block transfer mode

         MibSPI1INT0 = 0x00010000;           // enable DMA request (no ISR will be triggered)
    MibSPI1DAT1 = spi1dat1;             // kick off first 16-bit write

 

I was thinking that the DMA channel 0 will pickup to write additional data to SPIDAT1 ... but this is not the case.

Please help.

 

 

  • Hello Chuck,

    Can you please check if the following post help you?

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/250673.aspx

    Regards,

    Qingjun

  • Hi Qingjun,

    Yeah, I branched it correctly, SPI1 TX request line #1 to DMA internal channel 0, as follow:

    DMADREQASI0_bit.CH0ASI  = 0x01;         // channel 0:  request line #1 from MibSPI1 TX request

    I also branched RTI event1 request line #13 to DMA internal channel 15, to trigger the CRC module, and it is working properly.

    DMADREQASI3_bit.CH15ASI = 0x0D;         // channel 15: request line #13 from RTI event1

    Let me probe the SPI1 SIMO with a logic analyzer and get back to you. In the meantime, if you see something, please let me know.

    Regards,

    Chuck.

  • So my scope indicates that only the first dummy byte was shifted out by the SPI1 (see below), and the next byte never comes, supposedly handled by the DMA. Below is the steps that I have programmed:

    1. Configure SPI
    2. Configure DMA (as in my listing above)
    3. Enable DMA request in MibSPI1INT0 by setting bit #16
    4. Write a dummy byte to MibSPIDAT1 with CSHOLD=1
    5. Dummy byte was outputted correctly, but nothing else. The DMA should pickup on the TX_EMPTY and transfer more than 20 bytes.

    And problem that you can see in my procedure?

    I also tried to instruct DMA to write to MibSPI1DAT0 instead of MibSPI1DAT1, but still not working.

  • Hi Chuck,

    It is hard to see the problem from your post. Can you add DMA reset and and DAM enable before configuring DAM registers?

    DMA enable is the 16th bit of the global control register, and the DMA reset is 1st bit of the global control register. 

    Regards,

    Qingjun

  • Qingjun,

    I'm using IAR EWARM defined register name, sorry if that makes you confused.

    From my first post, first line of the code is the DMA disable and fifth line is DMA enable (GCTRL bit #16). Is the SW reset bit #1 set to 1 mandatory or upon power-up, the initial DMA reset is performed by default and automatically?

    Thanks.

    EDITED: Beside that, by reading the debugger registers window, I believe that all registers hold the configured values ... have to check tomorrow to be sure 100%

  • Hi Chuck,

    I am writing a project to test, and will come back to you later.

    Regards,

    QJ