RM48HDK EMIF Read delay issue in between two consecutive read cycles

Hi,

I'm using RM48 HDK with L950. In order to get the external ADC readings, I've connected the EMIF to a ADS85xEVM board. Here's the setup I have for the EMIF:

EMIF clock is 100MHZ. The EMIF MPU region is configured to be Device Type.

EMIF configuration register is initialized as:

emifREG->CE4CFG = (1U << 31U)|
                      (0U << 30U)|
                      (0U << 26U)|
                      (0U << 20U)|
                      (0U << 17U)|
                      (1U << 13U)|
                      (4U << 7U)|
                      (0U << 4U)|
                      (2U << 2U)|
                      (emif_16_bit_port) ;

For testing purpose, the code to read all the eight ADC results is simply written as:   
         AdcRaw[1]= ExMemAddr[1];
         AdcRaw[2]= ExMemAddr[2];    
         AdcRaw[3]= ExMemAddr[3];
         AdcRaw[4]= ExMemAddr[4];    
         AdcRaw[5]= ExMemAddr[5];
         AdcRaw[6]= ExMemAddr[6];    
         AdcRaw[7]= ExMemAddr[7];

With this setup above, I observed that the read cycle takes about 50ns. But to my surprise, the delay in between the  two consecutive read is about 180ns. To complete the eight reads, it takes about 1.7us in total from the first read cycle to the last one.

Is the delay in between the two consecutive EMIF read normal? Any suggestion to improve the speed?

Thanks,

Holly