synchronous update of PWM compare register

Andy,

I have forwarded your post to one of our experts on ePWM. He will be responding soon.

Regards,

QJ

The purpose of Shadow register is to prevent you update the period or duty cycle when it is comparing. In other words, these registers will be updated (write to the active register ) at strategic points ( e.g. when the counter is zero). Now, if you write ePWM1 0.1 us before this point and write ePWM3 0.1us after this point, only CMPA will be updated.

To avoid this, you need to make sure that your code is fast enough to update the ePWM before this point. Usually, that means the time of the algrithm to update the epWM < period.

Regards,

Haixiao

Hi,

if I understand that right, I have no chance to update the two registers
out of 'main'-execution level (not in interrupt) of my application without the risk of glitches.

I also thought of using the counter 'overflow' interrupt of the ePWM to write those
registers - is that what you meant?

Best regards,

Andy

I think so too.

You could do sth complicated to avoid this, for example,

1) setup another epwm interrupt 2us before the counter go back zero.

2) in the ISR, check if both the ePWM1 and ePWM3 data are ready. If yes, write both of them into the shadow register. If no, do nothing.

In most cases, you actually are 100% sure that the data will be ready, then, it is not necessary.

Prior to this device, we use NHET (a timer also available in this MCU) to generate PWMs, what we did is (No interrupt is needed):

BR .../* check the counter to see if it is zero*/

DJZ..../* once both pwm1 and pwm3 are ready, CPU write a 1 to this location*/

/*update the cmp*/

Regards,

Haixiao