Stellaris Launchpad Speed limitations

As far as I can tell, the stellaris (at least the Launchpad) Sysclk would easily handle this. I believe it's spec'd to 80 MHz and most code examples that I've found for it implement a 50 MHz clk, I'm guessing for stability purposes. Here's a link to the ARM that comes on the Launchpad, any hardware specs that you want to find out about should be in those documents: http://www.ti.com/product/lm4f120h5qr . I haven't done much with interfacing with external ADC/DAC and I'm just curious, which protocol were you planning to interface with the ADC/DAC, something like SPI, UART, GPIO, or something else?

Jordan,

The Stellaris launchpad LM4F120 is capable of running at a maximum of 80Mhz, it should be more than powerful enough for what you want to do.

Best of luck,

-Austin

This reporter not quite ready to jump upon launchpad band-wagon for this Ap.

You should be able to harness 12.288MHz output clock via Stellaris Timer - config'ed as PWM and set to 50% duty cycle.

Concern centers upon restrictions/processing demands placed upon Stellaris by stated 2.304MHz  "bit-clock."  Believe devil lurks - "this detail" - and greater study may prove worthwhile.

Note that PCM4204 sprang from distant Burr-Brown acq. - and that device is now 10 years old.  In this interim - newer devices may have dawned - with eased interface requirements. 

Idea of interconnecting humble, connector-eating launchpad to a 24 bit - broadcast quality ADC - may merit bit more consideration...

Thank you all for your help!  Here is my current plan:

• Switch to PCM4201 so I am only dealing with reading 1 channel per frame.  
• Run Stellaris @ 75MHz
• Use Split Timers loaded with 5  and 2 to get 12.5MHz 50% duty PWM for the ADC/DAC system clocks (256 * Fs)
• Use Split Timers loaded with 23 and 11 to get 3.125MHz 50% duty PWM for the bit clock (64 * Fs)
• Use Normal Timer loaded with 1535 to trigger sampling ISR at ~48.8KHz (Fs)

Assuming the PWM is done at the hardware level and doesn't use any processor cycles (perhaps I am wrong here) then my ISR would have 1536 cycles to transfer ADC/DAC data to and from the buffer as well as do calculations before it's called again.

My concern with this is being able to move data from GPIO to registers synchronously with the bit clock.

As far as I can tell from the data sheet, you are limited to which system clocks you can use. I believe using the PLL, the top three clocks you can get are the 80 MHz, 66.6 MHz, and 50MHz, and again, most of the code I've seen uses the 50MHz for what I can tell are stability purposes. I don't know if this will accomplish exactly what you want but for moving data from GPIO to registers, the LM4F has a very nifty feature called uDMA. Basically it moves data directly from GPIO to memory without ever talking to the processor, whenever there is data to be moved. You could in effect create a buffer in memory using it. As to the rest of the setup, it sounds reasonable, but I can't really speak to whether or not it will work for sure because I simply don't have experience trying it. I would highly recommend going to the link I posted and reading the data sheets and user guide. There is a lot of information there to sift through, but it should have most of your answers.

Points you may wish to consider:

a) Run Stellaris @ 75MHz - MCU manual outlines which external xtals enable certain PLL frequencies.  Our LX4F manual shows 66.67, 50, 40, 33.33MHz as more normal/customary System Clock frequencies - obtained w/standard xtal values.  (i.e. 66.67 achieved via /3 divisor, 50 achieved via /4 etc.)

b) Use Split Times loaded w/ 5 and 2 to get 12.5MHz, 50% duty.  Can't follow your math here - 50% duty results when your "match set" is 1/2 of "load set" - thus your settings seem outside this guide.

c) Similar comment toward your 3.125MHz - 50% duty creation.

Your final concern (moving data timely/properly) to sync w/bit clock - was my point in first writing.  I'm hard pressed to see this being achieved.

Update: Matt D's post (just above) had not hit forum as I was composing.  Never try to duplicate - my (a) must serve as "back-up" for Matt's earlier writing.  And indeed - as he notes we/others have had issues @ certain frequency "bands" beyond 50MHz.  (latest/greatest errata is best source for "admitted" limitations)

Assume you have rejected suggested search for a more modern, more data "forgiving" - broadcast quality ADC...  Someway, somehow "broadcast quality" and stripped-down launchpad MCU seem "less" than "match made in heaven..."  Far superior Stellaris MCUs exist...  (and may be populated upon boards less likely to "disgorge" their power inlet...)

In regard to the PWM math, I was under the impression that the timer counts from the loaded value down to 0 and the waveform toggles when the timer hits the match set value.  So the first value 5 would yield 6 cycles to count down (5,4,3,2,1,0).  Then when the timer hit the match set value 2 it would switch.  So 5,4,3 would be positive half, 2,1,0 would be negative.

I am definitely open to other ADC/DAC recommendations, I was citing these as they are what is suggested under "Audio ADC" here http://www.ti.com/lsds/ti/analog/audio/audio_overview.page

Thanks again for the time and effort here It is very much appreicated!

PWM Math:
May have, "opened mouth - inserted foot" here.  (and not - 1st/only time...)   In (pathetic) defense - usually use 3-4 digit values - to realize ~20KHz PWM frequency.  Will load/test/report later.

Reluctant to suggest alternatives - did want the 10 year age of chosen device to register - as the strict demands of that device impact all of your subsequent planning. 

Too often we note "incomplete up-front consideration/selection" yields sub-optimal results...  And aggravation - mis-directed effort...