.bss -> EMIF SDRAM

Do you have an example project with BSS in external memory?

Hi,

I have forwarded you thread to an expert in the team. They will be responding shortly.

- Forum support

Hi Pierre,

1- Txsr is not referenced in the datasheet, what should be its value?

>> This is mentioned in the "SELF REFRESH" section of the SDRAM datasheet to be the same as trc.

2- Where does emif_SDRAMInit() should be called? (for .bss section, then before global declarations).

>> You need accesses to the .bss memory region defined before performing initialization of global / static variables.

3- What is the maximal frequency for Emif_clk?

>> 100MHz for EMIF_CLK is not supported. Maximum EMIF_CLK frequency specified is 66.67MHz.

5- Maybe the conflict on ball D17 (pinmux)?

>> The multiplexing on D17 allows you to use this terminal either as a write-enable (nWE) or as a combined RnW (Read when '1, Write when '0') signal. This SDRAM requires a nWE signal, so you do not need to change the multiplexer configuration for D17.

Please slow down the EMIF_CLK frequency by slowing down the VCLK3 domain frequency. Let me know if this helps.

Regards, Sunil

Thanks Sunil! I tried with VCLK3=66.67MHz, then with 10MHz (=> Twr = 200ns). Still the same problems.

In sys_startup.c if I call emif_SDRAMInit() after systemInit(), variables in SDRAM are null. If call enif_SDRAMInit() before systemInit(), variables in SDRAM = 0x009C009C (?!?!?)

About software, do I have to do anything else than calling emif_SDRAMInit() to make SDRAM work? Is there a process to read/write (I don't know, considering timing or parsing data)? Do I have to run other init (setting all SDRAM's bit to 0)?

About hardware, Is the SDRAM 1024-page-sized? The datasheet says that, whereas several forum-topic specify 256. Is there an other driver than EMIF which should be enabled?

Do I have to enable some interrupts?

I "up" this topic.

Can you help me please?

Regards and thanks,

Pierre.

Pierre,

Some EMIF signals are multiplexed with other functions. These need to be configured correctly for the EMIF functions to be output on the assigned terminals. HALCoGen will generate this code for you when you configure the PINMUX tab. Also, there are 8 EMIF outputs that are gated off using the system module GPREG1 register bit 31. You need to set this bit for those 8 EMIF signals to be output on the assigned terminals.

No interrupts are necessary to be able to use the EMIF.

Regards, Sunil

I really don't know what to do, variables in .bss (i tried with sections .sysmem and . const too) are still null.
In CCS, register GPREG1 = 0x805FFFFF

In Halcogen 3.05 :

Vclk3 = Emif_clk = 55MHz.
driver EMIF enabled
trc = 63ns
trp = trcd = 20ns
twr = 37 ns
tras = 49ns
trc = 63ns
trrd = 14ns
txsr = 63ns
refresh period = 64ms
refresh cycles = 4096
cas = 2
banks = 4
page size = 256
PINMUX : checkbox "EMIF" enabled, "Gate off EMIF_clk" disabled.

In CCSV5 :

I call emif_SDRAMInit() and set 31th bit of GPREG1 in sys_startup.c, just after systemInit() (but the result is the same when i call this in main() ), where muxInit() is called :
emif_SDRAMInit();
systemREG1->GPREG1 |= (unsigned int)(1<<31);

I also tried to set PIMMR29[8] but nothing changed (also, the register doesnt seem to change). Thanks to p.222 of http://www.ti.com/lit/ug/spnu503a/spnu503a.pdf :

• EMIF_CLK Control:
PINMMR29[8] is set by default. This is used to block the EMIF_CLK from being output from the
microcontroller. If the EMIF is used to connect to an external SDRAM module, then the application must
enable the EMIF_CLK output by clearing the PINMMR29[8] bit.