Hello,
Our group is still somewhat new to the Hercules family of processors so we are still discovering things related to the chip architecture. I have a few questions that I am hoping some TI experts can help us with.
The main concern I have is that we recently found out that there are 12 wait states applied between consecutive reads of data from peripherals including the EMIF. We were told that we can mitigate this by getting it to work in Burst mode by creating 64-bit data pointers and reading all 64 bits out consecutively such that the 12-wait states only applies between reads of 64-bit values. This works ok for our use with an external ADC on the EMIF data bus, but I'm not completely clear on how to minimize wait state delays with other peripherals.
1) We intend to use CAN on our product. It is likely that we will have multi-frame data messages sent out over CAN. Are we going to suffer the same wait-state delays when processing messages from other nodes that get received and loaded into the CAN RAM buffers? If so, what is the recommended approach to either mitigate the delays, or at least reduce the CPU overhead... ie. would we use the DMA to move the message into regular RAM so we can process it there?
2) We also intend ot use SPI or I2C to connect to a serial EEPROM. What is the recommendation for accessing blocks of memory from such a device to minimize CPU load, or delay due to these wait states? I see that SPI has message RAM, but I2C does not. Should that lead into our decision to either choose I2C or SPI?
3) For the internal ADC, there are 24 channels so we could set it up to do a DMA transfer of the ADC results once we have converted all the channels. How long should we expect it to take to move all 24 channels into RAM?
Please correct me if I have mis-stated anything or am confused about when and how the wait states apply on this chip.
Thank you.
Jeff
