MibADC

Hi,

I have forwarded you thread to an expert in the team. They will be responding shortly.

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Hello Rustin,

Your calculations are correct, with one important correction required. The RM48L950 datasheet is a preliminary datasheet and includes target specifications that are not characterized. The RM48L952 datasheet includes updates to the specifications post-characterization. You can refer to this datasheet for the time being.

Assuming that your VCCAD supply is 5V nominal and the input voltage is 4.096V, the applicable IAIL specification is 250nA per channel. This should help reduce the error significantly.

Regards, Sunil

Application Note SPNA118B (ADC Source Impedance for Hercules ARM Safety MCUs) discusses in great detail ADC inaccuracies due to charge sharing, but makes no mention of inaccuracies due to source resistance (outside of the recharging time of Cext).  The app note goes so far as to give methods for getting down to fractions of an LSB in accuracy and Table 1 shows Rsource values of 200, 2K, and 20K that would allow this.  Section 11 lists the only consequence of high source impedance as being a time lag in channel response.

If we go off of the calculations from the datasheet, we see 250nA per channel for input voltage that is 300mV off of each rail or 1uA down to each rail.  If we assume 250nA per channel, multiply by 39, we get 9.75uA of leakage current for the channel being sampled.  The mux resistance of 250 ohms would generate error of 2.44mV.  A reasonable source resistance as shown in Table 1 of the app note of 2Kohm would generate an error of 19.5mV, 20K would generate an error of 195mV.  The 2K source resistance results in 4LSB error (16 counts – assuming VREFHI = 5V and 12-bit resolution) while the 20K source resistance results in over 7LSB error (160 counts).  Is this correct?  If so, why would an app note be written about charge sharing and getting down to fractions of an LSB when the leakage current of the input being sampled will result in multiple LSBs of error even with the internal mux resistance by itself, not to mention source resistance?  This doesn’t seem reasonable.

Also, why is the multiplier 39?  I only see 24 ADC channels.

Rustin,

I am sorry I missed the question in your last post. There are 16 dual-input channels and 8 single-input channels on this MCU. This makes a total of 40 input channels that all contribute towards the leakage calculations, hence the 39 multiplier.

Also, your observations and comments regarding the ADC Source Impedance app note are fair. We do need to update this document and include the effect of leakage on the conversion accuracy.

At this point, it will be worthwhile to consider the effect of adding an external capacitor very close to the ADC input terminal. The following table shows the error due to "on-state" leakage on the input channels.

As you can see, adding even a small external capacitance makes a big impact on reducing the error due to the input channel leakage. Please let me know if you have any questions on the above calculations.

Regards, Sunil

OK, this makes more sense.  The IAIL is the on-state leakage only for the period of time when the ADC input is being sampled, thus an external capacitor can minimize these effects.

Follow-up question:  Is there any constant input leakage for these ADC pins outside of this on-state IAIL value?  For example, some amount of pin leakage regardless of whether or not the pin is being sampled plus the transient on-state leakage (IAIL).

Rustin,

The IAIL specification is the leakage for each analog input pin, regardless of whether the pin is being sampled or not. This is described as the "Analog off-state input leakage current per channel" in the RM48L952 datasheet.

As shown in the ADC Input Equivalent Circuit diagram, when a single input is being sampled, the combined input leakage for all other open inputs needs to be accounted for. Hence the (40 - 1), or 39 multiplier in the calculation of the on-state leakage current for any given input channel.

Regards, Sunil

OK, I think I got it.  So, just to verify…

IAIL is present no matter what.  This jumps up to 39*IAIL only during the sampling period of the A/D pin being sampled.  If no external capacitance is provided, the minimum leakage would be IAIL and the maximum leakage would be 39*IAIL for any A/D pin.

Adding an external capacitor would reduce the maximum leakage to some value between IAIL and 39*IAIL depending on the equivalent impedance it presents to the channel being sampled (and using the formula previously presented).

Does this sound right?

Thank you!