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Hi all,
I have a strange behaviour of my MIBSPI1 with DMA (compatibily mode). Problem is that I lose last byte. It looks like that DMA BTC interrupt occurs too quickly.
My setup on RM48L952ZWT:
I have clk of 100Mhz, prescale set 9.
Functional pins are CLK, SOMI, SIMO.
Im SPI1 is in master mode.
First question: Do I have to send first byte manualy when im in master mode?
This is how i setup my spi to transfer dma:
/* Disable SPI DMA request */
SpiBase->DMAREQEN = 0x0u;
/* Disable SPI1 */
psSpiBase->ENA = 0x00u;
/* Disable DMA Channels based on SPI peripheral */
dmaSetChDisable(DMA_MIBSPI1_TX_CHANNEL, DMA_HW);
dmaSetChDisable(DMA_MIBSPI1_RX_CHANNEL, DMA_HW);
dmaReqAssign(DMA_MIBSPI1_RX_CHANNEL, DMA_MIBSPI1_0_REQ_LINE);
dmaReqAssign(DMA_MIBSPI1_TX_CHANNEL, DMA_MIBSPI1_1_REQ_LINE);
/* Enable interrupt for DMA channel - Block transfer complete */
dma_ntEnable(DMA_MIBSPI1_RX_CHANNEL, DMA_BTC);
/* Set configuration for DMA channel */
dmaTx.SADD = (uint32_t)&SrcBuff[1u];
dmaTx.DADD = (uint32_t)&SpiBase->DAT1.DAT1all;
dmaTx.FRCNT = Size-1u;
dmaTx.ELCNT = 1u;
dmaTx.ELDOFFSET = 0u;
dmaTx.ELSOFFSET = 0u;
dmaTx.FRDOFFSET = 0u;
dmaTx.FRSOFFSET = 0u;
dmaTx.PORT = 4u;
dmaTx.RDSIZE = DMA_ACCESS_8_BIT;
dmaTx.WRSIZE = DMA_ACCESS_8_BIT;
dmaTx.TTYPE = DMA_FRAME_TRANSFER;
dmaTx.ADDMODERD = DMA_ADDR_INC1;
dmaTx.ADDMODEWR = DMA_ADDR_FIXED;
dmaTx.AUTOINIT = DMA_AUTOINIT_OFF;
dmaRx.SADD = (uint32_t)&SpiBase->BUF;
dmaRx.DADD = (uint32_t)&DestBuff[0u];
dmaRx.FRCNT = Size;
dmaRx.ELCNT = 1u;
dmaRx.ELDOFFSET = 0u;
dmaRx.ELSOFFSET = 0u;
dmaRx.FRDOFFSET = 0u;
dmaRx.FRSOFFSET = 0u;
dmaRx.PORT = 4u;
dmaRx.RDSIZE = DMA_ACCESS_8_BIT;
dmaRx.WRSIZE = DMA_ACCESS_8_BIT;
dmaRx.TTYPE = DMA_FRAME_TRANSFER;
dmaRx.ADDMODERD = DMA_ADDR_FIXED;
dmaRx.ADDMODEWR = DMA_ADDR_INC1;
dmaRx.AUTOINIT = DMA_AUTOINIT_OFF;
/* Set configuration for DMA channel */
dmaSetCtrlPacket(DMA_MIBSPI1_TX_CHANNEL, dmaTx);
dmaSetCtrlPacket(DMA_MIBSPI1_RX_CHANNEL, dmaRx);
/* Enable MIBSPI1 */
SpiBase->ENA = 0x01;
/* manually send the first data, otherwise DMA doesn't work */
SpiBase->DAT1.DAT1all = SrcBuff[0];
/* Enable DMA channels */
dmaSetChEnable(DMA_MIBSPI1_TX_CHANNEL, DMA_HW);
dmaSetChEnable(DMA_MIBSPI1_RX_CHANNEL, DMA_HW);
/* Enable SPI DMA request */
SpiBase->DMAREQEN |= 0x1u;
Did someone had the same problems?
I must say that on slave side with this implementation works normal but i use SPI3.
Hi Dejin,
Are you losing the last bytes of the Transmit or receive?
If it is the transmit, can you please try to enable DMA channel before enable MIBSPI?
Hi Henry,
I lost in receive, but now i tried from different computer and enable DMA channels before enable MIBSPI without manually sending first byte and its working.
If i dont enable DMA channels before mibspi, DMA doesn-t work. i never get BTC RX interrupt
Thanks.
Hi all,
This problem is back. Some time from the starts its working and after while it lose the first receive byte.
We are using RM48L952ZWTT. Revision B.
We are sending over DAT0 register and CS and ENA signal are set as GPIO.
Could you please give the proper procedure for setting the DMA.
Hi Dejan,
I am looking into this issue and will get back to you tomorrow after first trying to duplicate your observation.
Regards, Sunil