PWM timing problems

Tim Mulder

Other Parts Discussed in Thread: RM48L952, HALCOGEN

Hi all,

I'm currently implementing several NHET PWM channels using the NHET CNT & MCMP instructions on a RM48L952. NHET is running at CPU speed, 220 mhz. I use a sample rate of 2500, which results in 1375 LR and 64 HR cycles per sample.

To adjust the PWM output, I use the RTI at a 0.4 ms interval to write different value to the HET memory. The whole isr with only one channel takes only 320 cpu cycles, so isr time << sample time. However, if I send a simple block wave (one sample high, one sample low, rinse and repeat), I only get small downward spikes of approx. 580 ns instead of 400 us. The rest of the time, the signal is high.

If I lower the RTI frequency to once every 0.8 ms, I get alternating low and high periods, but in a ratio of 1 : 3 (400 us vs 1200 us). I thought this may have to do with my isr taking too long, but even with one channel (320 cycles) it happens, so this cannot be the case. I also do not use the HTU, but since the isr only takes 320 cycles, that should not be the problem I guess?

I suspect I'm missing something trivial, but this has made me question my sanity at times.

Thanks in advance!

Regards,

Tim

over 12 years ago

0 Zhaohong Zhang over 12 years ago

TI__Mastermind 22715 points

Tim,

First of all, NHET runs from VCLK. It is limited to 100MHz per our spec. I would suggest you setting HCLK (cpu clock) to 200 MHz and set VCLK = HCLK/2 to get 100 MHz VCLK.

You need to be careful in adjusting PWM period and duty cycle. The reason is that NHET and CPU operates asynchronously. To avoid glitches in PWM, The parameters for CNT and MCMP should be updated when the CNT instruction reaches its max count value. The recommend method is to use MOV32 instruction. CPU writes to the data field of MOV32 instruction as its wish. You can set up NHET micro code so that MOV32 instruction moves new data to CNT and MCMP instructions when CNT instruction reaches its max value.

Thanks and regards,

Zhaohong

0 Tim Mulder over 12 years ago in reply to Zhaohong Zhang

Intellectual 600 points

Thanks for your reply! I set VCLK2 to 110 mhz (which should be okay, according to spns177a) by changing hetREG1/2->PFR from (6U << 8U) to (5U << 8U) and systemREG1->CLKCNTL from (0U << 24U) to (1U << 24U), but now the board hangs at het1ParityCheck(), where "NHET1 RAM parity error was not flagged to ESM.". This behaviour does not occur when running at out of spec speeds.

Regards,

Tim

0 Zhaohong Zhang over 12 years ago in reply to Tim Mulder

TI__Mastermind 22715 points

Tim,

Do you initialize NHET RAM? You should initialize all peripheral RAMs before using them.

Thanks and regards,

Zhaohong

0 Tim Mulder over 12 years ago in reply to Zhaohong Zhang

Intellectual 600 points

Yes, memoryInit() did run. The only things I changed are in my earlier post, plus "#define VCLK2_FREQ 110.000F" in system.h, but that does not seem to be used anywhere. Reverting the changes makes in run again, while nothing is changed regarding RAM initialization.

Kind regards,

Tim

0 Zhaohong Zhang over 12 years ago in reply to Tim Mulder

TI__Mastermind 22715 points

Tim,

I am wondering how you actually control the clock. Can you enable the ECLK in normal mode so that I can see VCLK/2 at ECLK pin?

Thanks and regards,

Zhaohong

0 Tim Mulder over 12 years ago in reply to Zhaohong Zhang

Intellectual 600 points

I used halcogen to generate a new project identical to what I used as a basis for mine, except with a VCLK2 divider of 1 instead of 0 (110 mhz vs 220 mhz). Then I used diff to get the differences, so I knew what I had to change in my real project.

I'll look into the ECLK in a bit. Thanks for your answers so far!

Regards,

Tim

0 Tim Mulder over 12 years ago in reply to Zhaohong Zhang

Intellectual 600 points

VCLK1 and VCLK2 both get their clock signals from PLL1. The VCLK1 divider is 5 (44 mhz) and the VCLK2 divider is 2 (110 mhz). I get a reading of 5.50040 mhz out of ECLK (VCLK1 / 8), so that seems correct.

Regards,

Tim

0 Sunil Oak over 12 years ago in reply to Tim Mulder

TI__Mastermind 49120 points

Tim,

Please note that VCLK2 frequency must be an integer multiple of VCLK frequency. This requirement is stated in the reference manual in the table that describes each clock domain on the MCU.

Regards, Sunil

0 Tim Mulder over 12 years ago in reply to Sunil Oak

Intellectual 600 points

Sunil,

The VCLK2 frequency is 110 mhz (220 mhz / 2). Unless I misunderstood your question, it complies.

Regards,

Tim

0 Sunil Oak over 12 years ago in reply to Tim Mulder

TI__Mastermind 49120 points

Tim,

Your VCLK2 frequency is HCLK/2, which is 220MHz/2 = 110MHz.

Your VCLK frequency is HCLK/5, which is 220MHz/5 = 44MHz.

This does not meet the requirement of VCLK2 to VCLK frequency ratio being an integer. You can change the VCLK divider to be HCLK/4, or 55MHz.

Regards, Sunil

0 Tim Mulder over 12 years ago in reply to Sunil Oak

Intellectual 600 points

My bad, I changed it to 55 mhz, but the original problem persists. I will modify my N2HET program to an interrupt based flow to see whether that solves the problem.

Regards,

Tim

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PWM timing problems