Hello,
We are in the middle of debugging our own RM48L952 design.
We are using SDRAM and this leads me to the question: Is it correct how we interpret the datasheet for the RM48L952.
On page 87 in the datasheet from November 2012, table 4-31, "tclk minimum 15nS", which means 67MHz maximum clock frequency to SDRAM.
Is this correct?
The next parameter in the table says: "tw minimum 5nS (High or low)". This indicates that tclk could be 100MHz.
Is the 15nS correct and minimum timing for SDRAM clock?
Thanks in advance!
Michael c".)
