Other Parts Discussed in Thread: TMS570LS1227
Hi,
I'm using DMA for the TMS570LS1227.Below is the my to transfer and receive the DMA.
/*reset dma*/
dmaREG->GCTRL = 0x00000001;
/* enable dma */
dmaREG->GCTRL |= 0x00010000;
/* stop at suspend */
dmaREG->GCTRL |= 0x00000300;
/*Source Address*/
dmaRAMREG->PCP[0].ISADDR =(C_UINT32)&Lpp_WriteData[0];
/*Destinaton Address*/
dmaRAMREG->PCP[0].IDADDR =(C_UINT32)0xFFF7E53BU;
/*Initial frame transfer count & Initial element transfer count*/
dmaRAMREG->PCP[0].ITCOUNT = (C_UINT32)(((Luc_data_len)<< 16U) |1);
/*Channel Control Register*/
dmaRAMREG->PCP[0].CHCTRL = (0<<16)
| (0<< 14) /*Read element size is byte*/
| (0 << 12)/*Write element size is byte*/
| (0 << 8) /*A hardware request triggers one frame transfer*/
| (1 << 3 )/*Read Post-increment*/
| (0<< 1 ) /*Write Post-increment*/
| (0); /*Auto-initiation mode is disabled.*/
/*Destination address element index and Source address element index*/
dmaRAMREG->PCP[0].EIOFF =0;
/*Destination address frame index and Source address frame index*/
dmaRAMREG->PCP[0].FIOFF =0;
/*Source Address*/
dmaRAMREG->PCP[1].ISADDR =(C_UINT32)0xFFF7E537U;
/*Destinaton Address*/
dmaRAMREG->PCP[1].IDADDR =(C_UINT32)&GusRxBuffer[0];//(C_UINT32)&temp[0];
/*Initial frame transfer count & Initial element transfer count*/
dmaRAMREG->PCP[1].ITCOUNT = (C_UINT32)((Luc_data_len << 16U) |1);
/*Channel Control Register*/
dmaRAMREG->PCP[1].CHCTRL = (0<<16)
| (0<< 14) /*Read element size is byte*/
| (0 << 12) /*Write element size is byte*/
| (0 << 8) /*A hardware request triggers one frame transfer*/
| (0 << 3 )/*Read Post-increment*/
| (1<< 1 ) /*Write Post-increment*/
| (0); /*Auto-initiation mode is disabled.*/
/*Destination address element index and Source address element index*/
dmaRAMREG->PCP[1].EIOFF =0;
/*Destination address frame index and Source address frame index*/
dmaRAMREG->PCP[1].FIOFF =0;
/*************************************************/
/*Enable Global Interrupt for Ch 1*/
dmaREG->GCHIENAS = 3;
/*Assign PortB for channel 1 */
dmaREG->PAR[0] = (0x4 << 28U)
|(0x4 << 24U);
/* Assign DMA request 30 to Chan 1*/
dmaREG->DREQASI[0]= (31U <<24U)
|(30U <<16U);
/*FIFO B is bypassed*/
dmaREG->PTCRL |= (1<<18);
/*Enable Hardware triggering for channel 1*/
dmaREG->HWCHENAS = 0x3;
/*Enable Frame transfer complete interrupt*/
//dmaREG->FTCINTENAS = 0x2;
/*set interrupt enable */
sciREG->SETINT = (0U << 26U) /* Framing error */
| (0U << 25U) /* Overrun error */
| (1U << 18U)
| (1U << 17U)
| (1U << 16U)
| (0U << 24U) /* Parity error */
| (0U << 9U) /* Receive */
| (0U << 8U) /* Transmit */
| (0U << 1U) /* Wakeup */
| (0U);
while ((sciREG->FLR&0x4)==0x4);
and we are uisng below code to disable the DMA when the required transfer is done.
if((dmaREG->GINTFLAG &0x0003) ==0x00003)
{
/*Diasble Hardware triggering for channel 1*/
//dmaREG->HWCHENAR = 0x00;
Luc_DmaSuccess=C_TRUE;
}
but when im calling the dma transmit and receive function again the dma transfer is not happening.
Please check my code and suggest me if i'm doing wrong when DMA transfer is done.
Thanks,
Regards,
Silpa
