Hello
I'm having trouble with the code provided by Halcogen to test the Flash ECC reporting functionality, specifically the single bit testing. Here is the code extract from Halcogen.
/* Flash Module ECC Response enabled */
flashWREG->FEDACCTRL1 = 0x000A060A;
/* Enable diagnostic mode and select diag mode 7 */
flashWREG->FDIAGCTRL = 0x00050007;
/* Select ECC diagnostic mode, single-bit to be corrupted */
flashWREG->FPAROVR = 0x00005401;
/* Set the trigger for the diagnostic mode */
flashWREG->FDIAGCTRL |= 0x01000000;
/* read a flash location from the mirrored memory map */
flashread = flashBadECC;
/* disable diagnostic mode */
flashWREG->FDIAGCTRL = 0x000A0007;
/* this will have caused a single-bit error to be generated and corrected by CPU */
/* single-bit error not captured in flash module */
if (!(flashWREG->FEDACSTATUS & 0x2))
{
flashClass2Error();
}
... etc
flashBadECC is set to 0x20080000 as per the code provided.
This code works fine as long as I have no code at the address 0x80000, as soon as I put any code at this address the Halcogen code does not work! In fact the read of the mirror memory causes a 2 bit ECC error.
So my first request is for a solution to get the Halcogen code to work if I have code at 0x80000.
My second request if for better documentation and examples on how the ECC can be tested as per your safety manual. For example here are some confusing parts of the reference manual...
The ECC DIAGMODE=7 example in SPNU449A p255 does not follow the code example produced by Halcogen and it states that the syndrome can be set to 70h to corrupt data bit 62 whereas Table 5-3 p250 states D38, which i assume is single bit error on bit 38.
The description for the FPAR_OVR register in SPNU449A p287 contains confusing references to Figure 10 {46} Figure 2.7.3 {50} and a reference to page 340 which contains information on the STC control registers!
I would like to read the ECC memory for the FLASH but I am not sure where it is; SPNU449A p251 has an example in Figure 5.1 but it is confusing and incorrect as SPNS162 p71 states that the TI-OTP ECC is in the range 0xF00C000-0xF00C1FFF. Is the Falsh ECC data at 0xF0400000?
Some Background information:
I am using the Spectrum Digital XDS510 to program an HDK using CCS with the option to auto generate the ECC. I'm pretty sure the ECC values have been programmed because I have enabled ECC in the code and the code runs, If I unselect the auto generate ECC in the CCS debug options the code does not run (an exception occurs just after I enable ECC checking in the core).
Thanks for your help in advance
