LM4F232H5QD SSI/SPI

Hi

I want to interface SSI/SPI with External  MAX7456 over LM4F232H5QD EVM as master SSI1

I try to Init the SSI1 as Master For example like the SSIInit()  function...

And Set SSITransfer() to write and read data from the chip by SSI1 protocol.

I use for example SSITransfer(0x81, 1, pucCmd, 1); to read register 0x81 but I did not get data from the chip Why?

   
void SSIInit(void)
{
 unsigned long ulIdx;
    unsigned long ulDataTx[NUM_SSI_DATA];
    unsigned long ulDataRx[NUM_SSI_DATA];
    unsigned long ulindex;

    //
    // Enable the peripherals used by this example.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

    //
    // Enable processor interrupts.
    //
    IntMasterEnable();

    //
    // Configure the appropriate pins to be SSI instead of GPIO.  Note that
    // the chip select is kept as a GPIO to guarantee the appropriate
    // signalling to the Atmel device.
    //
    GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, SSI_CS);
    GPIOPinWrite(GPIO_PORTD_BASE, SSI_CS, SSI_CS);
    GPIOPinTypeSSI(GPIO_PORTD_BASE, SSI_CLK | SSI_TX | SSI_RX);

    // Enable port PD3 for SSI1 SSI1TX
    GPIOPinConfigure(GPIO_PD3_SSI1TX);

 // Enable port PD1 for SSI1 SSI1FSS
    GPIOPinConfigure(GPIO_PD1_SSI1FSS);

 // Enable port PD0 for SSI1 SSI1CLK
    GPIOPinConfigure(GPIO_PD0_SSI1CLK);

 // Enable port PD2 for SSI1 SSI1RX
    GPIOPinConfigure(GPIO_PD2_SSI1RX);

    //
    // Configure the GPIO settings for the SSI pins.  This function also gives
    // control of these pins to the SSI hardware.  Consult the data sheet to
    // see which functions are allocated per pin.
    // The pins are assigned as follows:
    //      PD3 - SSI0Tx
    //      PD2 - SSI0Rx
    //      PD1 - SSI0Fss
    //      PD0 - SSI0CLK
    //
    GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0);

    //
    // Configure and enable the SSI port for SPI master mode.  Use SSI0,
    // system clock supply, idle clock level low and active low clock in
    // freescale SPI mode, master mode, 1MHz SSI frequency, and 8-bit data.
    // For SPI mode, you can set the polarity of the SSI clock when the SSI
    // unit is idle.  You can also configure what clock edge you want to
    // capture data on.  Please reference the datasheet for more information on
    // the different SPI modes.
    //
    SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, 1000000, 8);

    SSIEnable(SSI1_BASE);

    //
    // Reset the PDC SSI state machine.  The chip select needs to be held low
    // for 100ns; the procedure call overhead more than accounts for this time.
    //
    GPIOPinWrite(GPIO_PORTD_BASE, SSI_CS, 0);
    GPIOPinWrite(GPIO_PORTD_BASE, SSI_CS, SSI_CS);

    //
    // Read any residual data from the SSI port.  This makes sure the receive
    // FIFOs are empty, so we don't read any unwanted junk.  This is done here
    // because the SPI SSI mode is full-duplex, which allows you to send and
    // receive at the same time.  The SSIDataGetNonBlocking function returns
    // "true" when data was returned, and "false" when no data was returned.
    // The "non-blocking" function checks if there is any data in the receive
    // FIFO and does not "hang" if there isn't.
    //
    while(SSIDataGetNonBlocking(SSI1_BASE, &ulDataRx[0]))
    {
    }

    //
    // Enable the SSI interrupt.
    //
    IntEnable(INT_SSI1);

}

//*****************************************************************************
//
// This will start an interrupt driven transfer to the SSI peripheral.
//
//*****************************************************************************
void
SSITransfer(unsigned char *pucDataOut, unsigned long ulOutCount,
            unsigned char *pucDataIn, unsigned long ulInCount)
{
    //
    // Save the output data buffer.
    //
    g_pucDataOut = pucDataOut;
    g_ulOutCount = ulOutCount;

    //
    // Save the input data buffer.
    //
    g_pucDataIn = pucDataIn;
    g_ulInCount = ulInCount;

    //
    // Compute the number of extra bytes to send or receive.  These counts make
    // the number of bytes transmitted equal to the number of bytes received;
    // a requirement of the SSI peripheral.
    //
    if(ulInCount > ulOutCount)
    {
        g_ulOutExtra = ulInCount - ulOutCount;
        g_ulInExtra = 0;
    }
    else
    {
        g_ulOutExtra = 0;
        g_ulInExtra = ulOutCount - ulInCount;
    }

    //
    // Assert the SSI chip select.
    //
    GPIOPinWrite(GPIO_PORTD_BASE, SSI_CS, 0);

    //
    // Enable the transmit and receive interrupts.  This will start the actual
    // transfer.
    //
    SSIIntEnable(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO);

    //
    // Wait until the SSI chip select deasserts, indicating the end of the
    // transfer.
    //
    while(!(GPIOPinRead(GPIO_PORTD_BASE, SSI_CS) & SSI_CS))
    {
    }
}