Other Parts Discussed in Thread: TMS570LS1227
Hello,
I'm developing the appllication for the TMS570LS1227.We have a 16MHz input crystal.From that we are genearating the 180MHz of CPU clock from the PLL.
The below is the configuration used for the PLL generation.
systemREG1->PLLCTL1 = 0xA0835900;
systemREG1->PLLCTL2 = 0x7FC07200;
And the divider for the Peripheral clock is like below:
systemREG1->VCLKR = 1U;
systemREG1->VCLK2R = 1U;
systemREG2->VCLK3R = 1U;
At this clock setting the Flash driver is working fine but SCI communication is not happening at 90 Mhz input clock and at 19200 bps.
But at 60MHz peripheral clock my SCI driver is working fine.
systemREG1->VCLKR = 2U;
systemREG1->VCLK2R = 2U;
systemREG2->VCLK3R = 2U;
Would like to know what is the problem at 90Mhz SCI input clcok?
Thanks.
Regards,
Silpa
