MibSPI Communication between two TMS570

Hi George,

Things to check:

  - You need to make sure all the pins you are using in SPI mode are configured as SPI Function (value 1) in SPIPC0.

  - Has the transfer group been triggered (in the slave too) by the TGxCTRL register?

  - Are the pointers in the TGxCTRL register setup correctly to point to the data you've written into the MibSPI RAM?

Regarding the RAM dumps in you remail, were these both from the slave side?  (i.e. the transmit dump is also from the slave).

If not please post the slave's transmit ram contents as well.

And if the above doesn't help;  please post a dump of the MibSPI control registers so we can go through them and look for a problem.

Best Regards,

Anthony

Thanks for the help Anthony;

  - You need to make sure all the pins you are using in SPI mode are configured as SPI Function (value 1) in SPIPC0.

** Using HalCoGen generated mibspi files.

  - Has the transfer group been triggered (in the slave too) by the TGxCTRL register?

** Using HalCoGen generated mibspi files with mibspiTransfer functions.

- Are the pointers in the TGxCTRL register setup correctly to point to the data you've written into the MibSPI RAM?

** Using HalCoGen generated mibspi files with mibspiGetData & mibspiSetData functions.

Regarding the RAM dumps in you remail, were these both from the slave side?  (i.e. the transmit dump is also from the slave).

** Both are from the Slave side.

If not please post the slave's transmit ram contents as well.

** -n/a-

And if the above doesn't help;  please post a dump of the MibSPI control registers so we can go through them and look for a problem.

MibSpi#5 Registers

0xFFF7FC00

00000001 01000000 00000000 00000000 00000200 0F0F0F0F 0001060F 0F00090A 0000000F 0000000F 0000000F 00000000 00000000 0F0F0F0F 00000000 00000000 80000000 80000000 00000000 0000000F 00005910 00005910 00005910 00005910 00000000 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00007F00 80700000 40700000 40700000 40700000 40700000 40700000 40700000 40700000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000C001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000105 00000000 00000219 00000003 00000200 00000500 00590059 00590059 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4A050305

0xFFF7FE00

MibSpip5   GlbCtrl0 0x00000001 Global control register 0 [Memory Mapped]   GlbCtrl1 0x01000000 Global control register 1 [Memory Mapped]   Int0 0x00000000 Interrupt Register [Memory Mapped]   IntLvl 0x00000000 Interrupt Level Register [Memory Mapped]   IntFlg 0x00000200 Flag Register [Memory Mapped]   Fun 0x0F0F0F0F Pin Control 0 [Memory Mapped]   Dir 0x0001060F Pin Control 1 [Memory Mapped]   DIn 0x0F00090B Pin Control 2 [Memory Mapped]   DOut 0x0000000F Pin Control 3 [Memory Mapped]   DSet 0x0000000F Pin Control 4 [Memory Mapped]   DClr 0x0000000F Pin Control 5 [Memory Mapped]   PDr 0x00000000 Pin Control 6 [Memory Mapped]   PDis 0x00000000 Pin Control 7 [Memory Mapped]   PSel 0x0F0F0F0F Pin Control 8 [Memory Mapped]   TxDat0 0x00000000 Transmit Data Register 0 [Memory Mapped]   TxDat1 0x00000000 Transmit Data Register 1 [Memory Mapped]   RxBuf 0x80000000 Receive Buffer Register [Memory Mapped]   Emu 0x80000000 Emulation Register [Memory Mapped]   Delay 0x00000000 Delay Register [Memory Mapped]   DefCs 0x0000000F Default Chip select Register [Memory Mapped]   DatFmt0 0x00005910 Data Format Register 0 [Memory Mapped]   DatFmt1 0x00005910 Data Format Register 1 [Memory Mapped]   DatFmt2 0x00005910 Data Format Register 2 [Memory Mapped]   DatFmt3 0x00005910 Data Format Register 3 [Memory Mapped]   TgIntVec0 0x00000000 Transfer Group Interrupt Vector Register 0 [Memory Mapped]   TgIntVec1 0x00000000 Transfer Group Interrupt Vector Register 1 [Memory Mapped]   SrSel 0x00000000 Pin Control Register 9 [Memory Mapped]   PmCtrl 0x00000000 Parallel/Modulo Mode Control Register [Memory Mapped]   MibSpiEna 0x00000001 MibSPI Enable Register [Memory Mapped]   TgIntEnaSet 0x00000000 MibSPI Transfer Group Interrupt Enable Set Register [Memory Mapped]   TgIntEnaClr 0x00000000 MibSPI Transfer Group Interrupt Enable Clear Register [Memory Mapped]   TgIntLvlSet 0x00000000 MibSPI Transfer Group Interrupt Level Set Register [Memory Mapped]   TgIntLvlClr 0x00000000 MibSPI Transfer Group Interrupt Level Clear Register [Memory Mapped]   TgIntFlg 0x00000000 Transfer Group Interrupt Flag Register [Memory Mapped]   TickCnt 0x00000000 Tick Cnt Register [Memory Mapped]   LTgPend 0x00007F00 Last Transfer Group End Pointer [Memory Mapped]   Tg0Ctrl 0x80700000 MibSPI Transfer Group Control Register 0 [Memory Mapped]   Tg1Ctrl 0x40700000 MibSPI Transfer Group Control Register 1 [Memory Mapped]   Tg2Ctrl 0x40700000 MibSPI Transfer Group Control Register 2 [Memory Mapped]   Tg3Ctrl 0x40700000 MibSPI Transfer Group Control Register 3 [Memory Mapped]   Tg4Ctrl 0x40700000 MibSPI Transfer Group Control Register 4 [Memory Mapped]   Tg5Ctrl 0x40700000 MibSPI Transfer Group Control Register 5 [Memory Mapped]   Tg6Ctrl 0x40700000 MibSPI Transfer Group Control Register 6 [Memory Mapped]   Tg7Ctrl 0x40700000 MibSPI Transfer Group Control Register 7 [Memory Mapped]   Tg8Ctrl 0x00000000 MibSPI Transfer Group Control Register 8 [Memory Mapped]   Tg9Ctrl 0x00000000 MibSPI Transfer Group Control Register 9 [Memory Mapped]   Tg10Ctrl 0x00000000 MibSPI Transfer Group Control Register 10 [Memory Mapped]   Tg11Ctrl 0x00000000 MibSPI Transfer Group Control Register 11 [Memory Mapped]   Tg12Ctrl 0x00000000 MibSPI Transfer Group Control Register 12 [Memory Mapped]   Tg13Ctrl 0x00000000 MibSPI Transfer Group Control Register 13 [Memory Mapped]   Tg14Ctrl 0x00000000 MibSPI Transfer Group Control Register 14 [Memory Mapped]   Tg15Ctrl 0x00000000 MibSPI Transfer Group Control Register 15 [Memory Mapped]   Dma0Ctrl 0x0000C001 MibSPI Dma Channel Control Register 0 [Memory Mapped]   Dma1Ctrl 0x00000000 MibSPI Dma Channel Control Register 1 [Memory Mapped]   Dma2Ctrl 0x00000000 MibSPI Dma Channel Control Register 2 [Memory Mapped]   Dma3Ctrl 0x00000000 MibSPI Dma Channel Control Register 3 [Memory Mapped]   Dma4Ctrl 0x00000000 MibSPI Dma Channel Control Register 4 [Memory Mapped]   Dma5Ctrl 0x00000000 MibSPI Dma Channel Control Register 5 [Memory Mapped]   Dma6Ctrl 0x00000000 MibSPI Dma Channel Control Register 6 [Memory Mapped]   Dma7Ctrl 0x00000000 MibSPI Dma Channel Control Register 7 [Memory Mapped]   Dma0Cnt 0x00000001 ICnt Register 0 [Memory Mapped]   Dma1Cnt 0x00000000 ICnt Register 1 [Memory Mapped]   Dma2Cnt 0x00000000 ICnt Register 2 [Memory Mapped]   Dma3Cnt 0x00000000 ICnt Register 3 [Memory Mapped]   Dma4Cnt 0x00000000 ICnt Register 4 [Memory Mapped]   Dma5Cnt 0x00000000 ICnt Register 5 [Memory Mapped]   Dma6Cnt 0x00000000 ICnt Register 6 [Memory Mapped]   Dma7Cnt 0x00000000 ICnt Register 7 [Memory Mapped]   DmaCntLen 0x00000000 Dma LARGE Cnt register [Memory Mapped]   UErrCtrl 0x00000105 Uncorrectable Parity Error Control Register [Memory Mapped]   UErrStat 0x00000000 Uncorrectable Parity Error Status Register [Memory Mapped]   UErrAddr1 0x00000219 Uncorrectable Parity Error Address Register [Memory Mapped]   UErrAddr0 0x00000003 Uncorrectable Parity Error Address Register [Memory Mapped]   RxOvrNBufAddr 0x00000200 Receive RAM Overrun Buffer Address Register [Memory Mapped]   IoLpbkTstCtrl 0x00000500 IO Loopback Test Control Register [Memory Mapped]   EXTENDED_PRESCALE1 0x00590059 Extended Prescale Register 1 [Memory Mapped]   EXTENDED_PRESCALE2 0x00590059 Extended Prescale Register 2 [Memory Mapped]   ECCDIAG_CTRL 0x00000000 ECC Control register [Memory Mapped]   ECCDIAG_STAT 0x00000000 ECC Diagnostic Status register [Memory Mapped]   SPIREV 0x4A050305 Revision ID Register [Memory Mapped] 

Thanks George,

I'll look through these now and see if I spot anything.

Best Regards

-Anthony

That was it !!!

Thanks, moving forward ....

Hi Anthony,

I'm working with George on this issue and had a few questions.

1) What is the relationship between SCS[3:0] (or /SPISCS[3:0] as defined in TRM 25.2.3) and the pin names MIBSPIxNCS[n:0] (as defined in the datasheet)?

2) Why does a value of 0xA in the data input register correspond to TG 10 rather than SCS[3] and SCS[1]?

3) We left the CS for unused TGs to the defaults set in HALCoGen which is the same value as the TG.  If a slave TG size is zero and assigned CS never goes low, does this interfere with the reception of non-zero sized TGs?

Thanks, Charlie Johnston

PS - We really appreciate your quick and accurate responses on this forum.  You seem to get assigned most of our questions, and we would be lost without your clarifications

Hi Charlie,

Charles Johnston said:

1) What is the relationship between SCS[3:0] (or /SPISCS[3:0] as defined in TRM 25.2.3) and the pin names MIBSPIxNCS[n:0] (as defined in the datasheet)?

It's a 1:1 mapping.   Sorry about the name change.   The IP has been around for quite some time (getting close to 15 yrs) and has been on the TMS470R1x, TMS470M, and TMS570 series of parts so lots of people have touched the doc over time.   I'll enter a doc feedback submission on this point.   Also, if you spot other problem feel free to point them out on the forum or submit the feedback via the 'Submit Documentation Feedback" link that's in the footer of each page of our TRMs/Datasheets.

Charles Johnston said:

2) Why does a value of 0xA in the data input register correspond to TG 10 rather than SCS[3] and SCS[1]?

Good question.   We have a section missing from our TRM that needs to be added describing how the MibSPI chip selects work in slave mode.

In master mode, you get to pick the chip select that is asserted by each transfer group by programming this into CSNR field of the transfer group's transmit data register in the MibSPI RAM.   So there is no apriori mapping between chip selects and transfer groups in master mode.

I should also add that in master mode you could program the CSNR field with a value of 0x0A and during the transfer it woudl assert both MibSPIxNCS[3] and MibSPIxNCS[1].  The MIBSPI doesnt' care if you want to use the chip selects as one-hot encoded or binary encoded or any encoding of your choice - it treats the CSNR field as just a 'pattern' to put onto the pins during the transfer.

What we missed is the description of how chip selects work in slave mode.    In slave mode, the mapping is a binary mapping between the MibSPIxNCS[3:0] and the TG#.

So the pattern '0000' selects TG0,  '0001' selects TG1,  '0010' TG2, and so on.  There is also a register "SPIDEF" that allows you to select the pattern that signifies all slaves deselected. 

Now, I believe we suggested a workaround to the previous problem which was to configure only one of the MibSPIxNCS pins as a 'functional' pin and the rest as GIO.   By doing that we are telling the MibSPI to ignore the other chip select pins and only look at the one pin you're interested in.   In that case, you've now only got TG0 that you can use as a chip select;  so the MibSPI looks like one slave SPI.

Charles Johnston said:

3) We left the CS for unused TGs to the defaults set in HALCoGen which is the same value as the TG.  If a slave TG size is zero and assigned CS never goes low, does this interfere with the reception of non-zero sized TGs?

This should also be taken care of by only enabling one chip select pin as functional.   There won't be any way to select any of the other TGs through the pins.

Charles Johnston said:

PS - We really appreciate your quick and accurate responses on this forum.  You seem to get assigned most of our questions, and we would be lost without your clarifications

 

Thank you that's always nice to hear.  And thank you for choosing the TMS570 product line when there are so many MCU choices available.

Thanks, Anthony.

It makes sense now.

Charlie Johnston

hello,i am from China。i am glad to to ask for ur help.i have two RM48952 boards with MIBspi5 connected  with wire. the one is as master,and the other is slave..i use halcogen to generate code. the only palce i alter is enable mibspi5 。

do u have example that two board communication with mibspi5? please send me!  thank u!  zhouranvipo@sina.com

list is my master and slave code

//master

void main(void)
{
/* USER CODE BEGIN (3) */
uint16 tx[8] = {0xAAAA,0xAAAA,0xAAAA,0xAAAA,0xAAAA};
uint16 rx[8] = {0};
mibspiInit();

mibspiSetData(mibspiREG5,0,tx);
mibspiTransfer(mibspiREG5,0);

while(mibspiIsTransferComplete(mibspiREG5,0) ==FALSE)
{
;
}

mibspiGetData(mibspiREG5,0,rx);

while(1);
/* USER CODE END */
}

//slave

void main(void)
{
/* USER CODE BEGIN (3) */
uint16 tx[16] = {1,2,3,4,5,6,7};
uint16 rx[16] = {0};

mibspiInit();

mibspiSetData(mibspiREG5,0,tx);
mibspiTransfer(mibspiREG5,0);

while(mibspiIsTransferComplete(mibspiREG5,0)==FALSE )// slave wait unitl data is coming!
{
;
}

mibspiGetData(mibspiREG5,0,rx);

while(1);
/* USER CODE END */

}

thank u!!!!!!!!!!