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SPI receive in compatibility mode

Mark Blay
Intellectual 370 points

Hi, I am having a problem with SPI receive in compatibility mode.

My application is successfully communicating over SPI interface. I have a function to receive data which selects a device and generates clocks while holding SIMO line low to clock in data from the slave. I then wait until RXEMPTY flag in RXBUF is cleared before reading data from the buffer.

But periodically my software is hanging as RXEMPTY is not getting cleared. I don't understand how this can happen, even if no device is present, generation of clocks should shift data into the device and then transfer to RXBUF.

What could be the problem to cause RXEMPTY not to get set? This is not happening all of the time but does always seem to be associated with one SPI bus (SPI5).

Thanks for your help,

Mark.

  • 0
    TI__Mastermind 22715 points

    Mark,

    SPI is doing synchronous transmission and reception. As a SPI master you need first to start a transmit in order to receive. You should start transmitting the new data after the previous received data is read. Do you keep the sequence as transmit-receive pairs?

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 370 points

    Hi Zhaohong , thank you for your response.

    Yes, I am observing this sequence.

    The sequence that immediately precedes the error is:

    Load DAT1, wait for TXFULL bit of SPIBUF to be clear, wait for RXEMPTY to be clear.

    But as I said, sometimes we wait forever at the last step and RXEMPTY bit of SPIBUF remains set. This only happens occasionally so I suspect maybe there is some marginal timing problem, but I can't see what it can be.

    Any suggestions would be appreciated.

    Thanks,

    Mark. 

  • 0 in reply to Mark Blay
    TI__Mastermind 22715 points

    Mark,

    You need to make sure that you should write new data to SPIDAT1 ONLY AFTER the previous received data is read from SPIBUF. SPI transmission will start immediately after SPIDAT1 is written. You will run into a racing condition if you use the following sequence.

    Load SPIDAT1 -> wait till TXFULL clear -> load SPIDAT1 -> wait till RXEMPTY clear -> read SPIBUF -> Load SPIDAT1 ...

    You may not see RXEMPTY clear because new data comes in due to the second write to SPIDAT1. Please remember the a register read takes 12 VCLK cycles.

    I would suggest using the following sequence in polling mode.

    Load SPIDAT1 -> wait till RXINTFLG set in the SPIFLG register (0x10) -> read SPIBUF -> Load SPIDAT1 ...

    Or Load SPIDAT1 -> wait till RXEMPTY clear -> read SPIBUF -> Load SPIDAT1 ...

    You need to make sure that you should write new data to SPIDAT1 ONLY AFTER the previous received data is read from SPIBUF.

    Thanks and reagrds,

    Zhaohong