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SPI/DMA throughput?

Jack Andrews
Intellectual 370 points
Other Parts Discussed in Thread: ADS1672

Hi,

I'm looking to read five 24 bit ADCs (the ADS1672) at 625KS/s simultaneously using an RM48.  I need to take 80 readings and then process the data as the next set of readings come in.  Does this seem plausible?  It would seem the SPI peripherals can run at this speed, but would the DMA be able to service all five peripherals fast enough?

If this doesn't seem possible, does anyone have any suggestions for a processor which might be up to the task?

Thanks,

Jack

  • 0
    TI__Intellectual 1480 points

    Jack,

    We are looking into your query but can you clarify/confirm  on a couple of points

    1) do all the 5 - 24 bit ADC's  have to be read in parallel by the RM48 MCU or can they be interleaved somehow

    2) regarding the no of reading to be processed , are the 80 reading for each one the 5- 24 bit ADC or  is it 80/5 which is 16 readings for each of the ADC's.

    -Hercules Forum support

  • 0 in reply to Hari Pendurty
    TI__Mastermind 22715 points

    Jack,

    You are able to connect one ADS1672 to one MibSPI module. DMA has enough throughput to move data between MibSPI RAM and system RAM. The regular SPI can only support 16 bit data.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Hari Pendurty
    Intellectual 370 points

    Hari Pendurty said:

    Jack,

    We are looking into your query but can you clarify/confirm  on a couple of points

    1) do all the 5 - 24 bit ADC's  have to be read in parallel by the RM48 MCU or can they be interleaved somehow

    2) regarding the no of reading to be processed , are the 80 reading for each one the 5- 24 bit ADC or  is it 80/5 which is 16 readings for each of the ADC's.

    -Hercules Forum support

    Hi Hari, thanks for our help.  To answer your questions:

    1) They have to be read in parallel - the data rate is too high to interleave

    2) There are 80 readings per channel which need to be made

    Zhaohong, if we did 3 x 8 bit reads, could the DMA service the standard SPI peripherals fast enough?

    Thanks,

    Jack

  • 0 in reply to Jack Andrews
    TI__Mastermind 22715 points

    Jack,

    I would not worry about DMA throughput. I am more worried about the compatibility of the interface.

    If we do a 12bitx2 read from regular SPI, (1) the CS pin will toggle at the end of first 12 bit transfer and (2) there will be a stretch on the SPI clock if SPI is the clock master. Is it acceptable to ADC operation?

    If we use a MibSPI module, we need to use two buffers (16bit and 8 bit) to collect one 24 bit data. We can hold CS low for the two buffers but the SPI  clock will also get stretched a little in the transition of those two buffers.

    If the above is acceptable, you can set up a 160x32bit buffer in the system RAM for each ADC. You can set up DMA block transfer of 160x32bit, enable HBC and BTC interrupts and autoinit. After HBc interrupt, you can process the first 80 samples and process the second 80 samples after BTC interrupt. DMA will restart by itself.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 370 points

    Hi Zhaohong,

    Thanks very much for your help.  Your MibSPI suggestion seems like a good idea - could you please explain how to alternate between the two transfer groups?  Note that the timing diagram for the ADC is as follows:

    So I would presume the trigger event on the first TG should be rising on a GIO (connected to DRDY) for the first 16 bits and then it should switch to the second TG for the next 8 bits.  I don't suppose clock stretching should be an issue.

    Also, would your suggestion be able to fit one set of 80 samples (80x12bit and 80x8bit) in multi-buffer RAM?  My understanding is that MBRAM is 16bit and you can't fit two 8 bit reads in one address?  Or am I missing something?

    For the regular SPI, would it be possible to emulate the chip select using GIO?

    Thanks,

    Jack

  • 0 in reply to Jack Andrews
    TI__Mastermind 22715 points

    Jack,

    I am afraid that there may be some misunderstanding. What I meant is to have two buffers in one transfer group. These two buffers will be located in MBRAM. You can use DMA to move data from MBRAM to a buffer located in system RAM. i have double checked ADS1672 datasheet, you can tie the CS low.

    The concern I have is how to synchronize the data conversion with SPI communication. If you use ADC1672 as a SPI clock master, The SPI clock will be continuous for the 24 bit data. you may need to do some experiment to makesure if MibSPI/SPI module could handle the 24 bit data  as multiple 16/8 or 8/8/8 bits the slave mode. it should be OK in theory because there are three stages of receive buffers.

    Thanks and regards,

    Zhaohong