ESM Error on TMDXRM48HDK

Hello Jamie,

Can you connect to the boards with JTAG and record which bits are set in the ESM error registers? Once we determine this we can figure out how best to approach the problem and/or determine if there are possible issues with startup code or hardware.

Here is one such output. This is an example where the het1ParityCheck has failed. If I #if 0 out the infinte while loop each subseqeunt parity check will fail too.

Esm    
    IflErrPinSet1    0x00000000    Influence Error Pin Set/Status Register 1 [Memory Mapped]    
    IflErrPinClr1    0x00000000    Influence Error Pin Clear/Status Register 1 [Memory Mapped]    
    IntEnaSet1    0x00000000    Interrupt Enable Set/Status Register 1 [Memory Mapped]    
    IntEnaClr1    0x00000000    Interrupt Enable Clear/Status Register 1 [Memory Mapped]    
    IntLvlSet1    0x00000000    Interrupt Level Set/Status Register 1 [Memory Mapped]    
    IntLvlClr1    0x00000000    Interrupt Level Clear/Status Register 1 [Memory Mapped]    
    Stat1    0x00000000    Status Register 1 [Memory Mapped]    
    Stat2    0x00000000    Status Register 2 [Memory Mapped]    
    Stat3    0x00000000    Status Register 3 [Memory Mapped]    
    ErrPinStat    0x00000001    Error Pin Status Register [Memory Mapped]    
    IntOffstHgh    0x00000000    Interrupt Offset High Register [Memory Mapped]    
    IntOffstLow    0x00000000    Interrupt Offset Low Register [Memory Mapped]    
    LtCnt    0x00003FFF    Low-Time Counter Register [Memory Mapped]    
    LtCntPre    0x00003FFF    Low-Time Counter Preload Register [Memory Mapped]    
    ErrKey    0x00000000    Error Key Register [Memory Mapped]    
    ShdwStat2    0x00000000    Status Shadow Register [Memory Mapped]    
    IflErrPinSet4    0x00000000    Influence Error Pin Set/Status Register 4 [Memory Mapped]    
    IflErrPinClr4    0x00000000    Influence Error Pin Clear/Status Register 4 [Memory Mapped]    
    IntEnaSet4    0x00000000    Interrupt Enable Set/Status Register 4 [Memory Mapped]    
    IntEnaClr4    0x00000000    Interrupt Enable Clear/Status Register 4 [Memory Mapped]    
    IntLvlSet4    0x00000000    Interrupt Level Set/Status Register 4 [Memory Mapped]    
    IntLvlClr4    0x00000000    Interrupt Level Clear/Status Register 4 [Memory Mapped]    
    Stat4    0x00000000    Status Register 4 [Memory Mapped]    

Hello Jamie,

Can you upload your CCS project that toggles the GIO and sets a PWM on an NHET pin? I will try it on my HDK and see what results I have in order to try and reproduce/debug the code.

Hello Chuck, please see attached. It is as simple as I can make a routine. I have a PWM configured through HALCogen to het1(29).

I get errors on ESM parity checks. If I don't get the error I do not see the PWM. The GIO bit will be set.

If you don't get an ESM error try executing a system reset from the debugger in CCS. That is a fairly repeatable way for me to end up with ESM partity errors since receiving the new board.

Thanks

JAmie0830.SIMPLELED.zip

Jamie,

I have ran the project on my RM48 kit and don't see any issues with the code execution. I can break and step through the gioSetBit function with no issues. Also, taking a closer look at your dump of the ESM registers, there are no ESM errors indicated in the ESM error status registers as I would expect if it is hanging at the while loop during the het parity check on startup. Can you comment out the entire call  to the HET parity check and see if the other parity checks continue to fail? i.e., can we isolate it to something related to the HET1 parity check routine?

Hello Chuck,

Apologies for the late reply but we had a long weekend here in BC.

I have been trying this morning to reproduce the failure and have not succeeded using the SIMPLELED build I sent you. I cannot explain why as nothing has changed.

As an aside I did note a bug in my nhet1 configuration which explained why I never got my PWM on pin nhet1(29). I had not set the IO direction to output on that pin. It is now working with pin 29 LED flashing on the HDK via the HET PWM driver and pin het1(0) held ON using a direct gioSetBit() routine.

As it will not reproduce in my reduced LED build I tried again with the parity checks enabled in my real application development. The error came back, failing on the het1parity check. Comment out the check and the next in line fails, het2, htu2, the adc parity checks did not fail but the vim parity check did. Do I have an initialisation problem or issue with my HALcogen configuration? I have attached the HALcogen project for your reference. So I can continue with my work I am keeping the parity checks disabled for now.

Thanks

Jamie

The HALcogen project : 5187.HAL_RDA-2.zip

Hello Jamie,

Unfortunately, I was not able to get back to your code to try an reproduce the issues you were seeing. Are you still seeing problems with it or have you been able to find the issue? Let me know the status so we can know how to proceed.

Hello Chuck,

This issue is an old one now and I cannot think on what caused it or how I may have inadvertently resolved it in the last months.

I have been working on our product PGE hardware for the most part therefore any latent issue I had with the ZWT builds could well be hidden.

Early next year we intend to review and enable all necessary diagnostics on our production hardware therefore i'll keep this open until we have successfully worked through that.

Jamie