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Accessing DMA working registers - Current Transfer Count Register (CTCOUNT)

Joe Josn
Expert 1285 points


Hello,

I am trying to acquire a 'lot' of data with 570LS1227. DMA is triggered in hw to transfer a 16 element burst every 3 us. I want to avoid any interrupts and I allocated a 1K deep buffer for the data. Instead of waiting for a periodic interrupt (HBC/BTC) I would like to poll DMA's working register to process any new data collected in the background loop. But none of the working registers are updated during/after the transfer! There is only one active DMA channel in the system during this test.

Is there any trick to update the active working registers?

Thanks,

Joe.

  • 0
    TI__Genius 11645 points

    Hello Joe,

    BTCFLAG register will be set once your block transfer is complete for the particular channel, irrespective of the interrupt being enabled or not.

    Set-up DMA for Hardware Request, so that it starts the transfer every time it gets a HW Request.

    Step-1: You can poll the BTCFLAG until it gets set which indicates the end of Block transfer.

    Step:2 : Once set, indicates the completion and you can clear the same by writing on to the same bit.

    Step:3 : Go to setp-1(Wait for the BTCFLAG to get set by the next HW Request).

    Let me know if this solves your problem.

    Best Regards,

    Karthik.

  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Expert 1285 points

    Thanks Karthik for the quick response, but not what I am looking for.

     I want to avoid waiting for the whole/half  block transfer to complete before processing the data. I have to process the data frames already transferred without taking a FTC interrupt and without waiting for the whole/half block complete status/interrupt.

    TRM SPNU515 section 16.2.4 DMA Channel Control Packet (page 549) shows the Primary and Working Control Packet for each DMA Channel. I should be able to tell from the working registers how many frames got transferred. It is not working as described in the TRM.

     Thanks,

    Joe

  • 0 in reply to Joe Josn
    TI__Genius 11645 points

    Joe,

    Now I get your problem. I believe you are trying to transfer 16 elements for every hardware req(happens every 3us).

    Can you help me with IFTCOUNT,IETCOUNT settings , also the TTYPE setting in CHCTRL for me to understand the issue better ?

    Best Regards,

    Karthik.

  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Expert 1285 points

    Karthik,

    I have 0x10 elements per frame, 0x600 frames in the block. (ITCOUNT=0x0600 0010)

    Transfer Type is 0 =Frame Transfer, Indexed 16bit Rd/Wr. (CHCTRL = 0x0000 501F)

    Issue is that the Control Packet Working Registers are not updated, ever!

    Thanks,

    Joe

  • 0
    TI__Mastermind 49120 points

    Joe,

    The DMA control registers PBACSADDR, PBACDADDR, and PBACTC respectively show the current source address, current destination address and current transfer count of the active channel. I believe this should help your application get the necessary information. You can tell the number of pending and active DMA channels by reading the DMASTAT register.

    If there is no case of arbitration between channels (as in your application), you can use these registers to determine the current status of the DMA transfers. If one channel does get arbitrated by the other, then you can use the information from the working control packets for the channel that gets arbitrated out.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Expert 1285 points

    Thanks Sunil for the TIP. When I have another active dma channnel, the working registers are updated upon arbitration. Thanks again.