How to sync ePWM1 using N2HET1_LOOP_Sync in champion

Hi Keyur,

I am assuming that you are referring to SPNU515, the TRM for TMS570LS12x/11x Hercules MCUs.

The timing synchronization scheme implemented on these MCUs requires that N2HET1 be used as the master time-base generator. For this, you must select N2HET1 to be a master by setting the "CMS: clk_master/slave" bit of the global control register (HETGCR, address = 0xFFF7B800).

The N2HET1 module, once configured as the time-base master, automatically outputs its loop-synchronization signal for the other timers to use. This is the N2HET1_LOOP_SYNC signal shown in figure 4-5 of SPNU515 on page 241. The connections between the N2HET1_LOOP_SYNC signal and the multiplexor for the ePWM1_SYNCI input are done internal to the MCUs. No external pin is used.

The N2HET1_LOOP_SYNC is leading the actual loop-resolution clock used inside the N2HET1 module by 2 VCLK2 cycles. This is due to the fact that the receiving timer module would double-synchronize the LOOP_SYNC signal before using it.

You need to set PINMMR36[25] and clear PINMMR36[24] in order for the SYNCI input to ePWM1 to be the N2HET1_LOOP_SYNC signal, as also shown in figure 4-5.

Section 19.2.2.3.3 starting on page 700 provides detailed information on how to synchronize the ePWMx modules using the ePWM1_SYNCI synchronization input signal.

Please let us know if any description is unclear.

Regards,

Sunil

Sunil,

Thanks for your reply.

I am referring SPNU515, the TRM for TMS570LS12x/11x Hercules MCUs. I did looked at figure 4.5 of SPNU515,

question 1: How does clearing PINMMR36[24] pin would affect, because I see only pin PINMMR36[25] select the N2HET1_LOOP_SYNC line.

question 2: Currently I am using N2HET1 and N2HET2 for different functions and already N2HET2 is select as master, so Is that possible to have both Master ?.

question 3: would you clarify for about "2 VCLK4 Pulse Strength  block" ? if I have LR=128, HR=1, so LR clock would be = 128*VCLK2, so this means every 128*VCLK2 + 2 VCLK4, N2HET1 send trigger to ePWM ? what clock frequency VCLK4 block taking in here ?

question 4: Is that possible to set trigger ePWM when counter value in N2HET1 reach without burning external pin ?

Hi Keyur,

See my comments below:

question 1: How does clearing PINMMR36[24] pin would affect, because I see only pin PINMMR36[25] select the N2HET1_LOOP_SYNC line.

>> You are right. PINMMR36[24] has no impact on the selection. You only need to set PINMMR36[25] to allow N2HET1_LOOP_SYNC to be used as ePWM1_SYNCI.

question 2: Currently I am using N2HET1 and N2HET2 for different functions and already N2HET2 is select as master, so Is that possible to have both Master ?.

>> A master/slave configuration is only required if the timer modules need to all be synchronized (have the same time base). If the two N2HET modules operate independent of each other, then the master/slave configuration has no effect.

>> One feature of the N2HET module is that it forwards the EXT_LOOP_SYNC out on the N2HET1_LOOP_SYNC when the N2HET1 module is configured to be a slave. This will allow you to even use the N2HET2 to be the master time-base genarator.

question 3: would you clarify for about "2 VCLK4 Pulse Strength  block" ? if I have LR=128, HR=1, so LR clock would be = 128*VCLK2, so this means every 128*VCLK2 + 2 VCLK4, N2HET1 send trigger to ePWM ? what clock frequency VCLK4 block taking in here ?

>> The loop-resolution clock frequency is defined by the HR and LR prescalers. As per your configuration, the LR clock period is 128 * VCLK2 period. This LR clock as well as the LOOP_SYNC signal (output by the N2HET module) are not 50% duty cycle clock signals. Rather, there is a high-phase that is 1 VCLK2 period wide, followed by a low-phase that is 127 VCLK2 periods wide.

>> The ePWM modules operate using the VCLK4 clock domain. There is no dependency between VCLK2 and VCLK4 clock ratios, other than they are both divided down from the HCLK clock domain. This requires the design to stretch the N2HET1_LOOP_SYNC signal to at least 2 VCLK4 periods to ensure that the LOOP_SYNC signal is latched inside the ePWM1 module.

question 4: Is that possible to set trigger ePWM when counter value in N2HET1 reach without burning external pin ?

>> This is not supported, as the LOOP_SYNC signal is in phase with the LR clock. The N2HET1[16] is multiplexed with the ePWM1_SYNCI function, so whatever you output on N2HET1[16] can be used as a synchronization input by the ePWM1 without any external connections. This is another option that is available, but does require you to actually output the sync signal on the pin.

Regards,

Sunil