FIFO control, when SSI slave mode

Hi,

Usually the FIFO is read/drained as to be sure of the first byte location. The code can be found in x_Ware/examples/peripherals/ssi/spi-master.c, but should be the same for a slave. Here it is the snippet:

//
// Enable the SSI0 module.
//
SSIEnable(SSI0_BASE);

//
// Read any residual data from the SSI port. This makes sure the receive
// FIFOs are empty, so we don't read any unwanted junk. This is done here
// because the SPI SSI mode is full-duplex, which allows you to send and
// receive at the same time. The SSIDataGetNonBlocking function returns
// "true" when data was returned, and "false" when no data was returned.
// The "non-blocking" function checks if there is any data in the receive
// FIFO and does not "hang" if there isn't.
//
while(SSIDataGetNonBlocking(SSI0_BASE, &ulDataRx[0]))
{
}

Also, some time ago was a thread about ssi slave - and someone from TI posted a small slave example - I did not recorded who was, but many thanks... this example is added here.

3240.spi_slave.zip

Petrei

Thanks for reply

But that's not enough for me

Host (SSI master) can send ssi data at any time,

so slave must know the first bytes to know the command, address, length which host transfered.

Is this SW design is impossible for Stellaris?

HI,

I understand your pain - but you must also take into consideration some things:

• a) microcontroller's speed is much higher than SSI speed (or you can choose/play with it).
• b) You must experiment first - for instance what is written in blue in my previous post and see if you can transfer/identify several bytes.
• c) Must refine your protocol... try to use interrupts - the .zip package program uses interrupts - could be (or not) a better idea - you must decide.
• d) SSI module is designed by ARM and is the same for all CM4 manufacturers.

Petrei

Glad that you persisted - achieved your objective.

That said - have you considered - or attempted - to "pre-seed" an initial byte w/in your LX4F's SSI TX FIFO - so that the Slave returns "valid/meaningful" data during the Master's initial byte transaction?  (you know that SSI sends & receives "together" - although perhaps on different SSI Clock edges)  This initial Slave byte may be the Slave Identifier - insuring that the correct Slave has come, "on-line" - which is helpful during "multi-Slave" environments.

If you can manage/cause this "pre-seeding" - the 1st byte returned by the Slave escapes "dummy" status - aiding system efficiency...

That's good idea.

I'll apply that in my source code.

Thanks, cb1_mobile

Hi,

Please share code here.

I am trying to communicate with NI cRIO (master) and tiva c (slave).

regards,

Krishnat