HalCoGen 03.05.00 (01) bug in DMM code generation

Hi Jiri,

We have forwarded your query to the Halcogen experts.

They will get back to you

Thanks,

Praveen

Hi Jiri,

Are you on HALCoGen version 03.05.02?

Can you give some more details of your problem. I see below definition which match the TRM.

uint32  GLBCTRL;    /**< 0x0000: Global control register 0         */
    uint32  INTSET;     /**< 0x0004: DMM Interrupt Set Register        */   
    uint32  INTCLR;     /**< 0x0008: DMM Interrupt Clear Register      */
    uint32  INTLVL;     /**< 0x000C: DMM Interrupt Level Register      */   
    uint32  INTFLG;     /**< 0x0010: DMM Interrupt Flag Register       */
    uint32  OFF1;       /**< 0x0014: DMM Interrupt Offset 1 Register           */
    uint32  OFF2;       /**< 0x0018: DMM Interrupt Offset 2 Register           */
    uint32  DDMDEST;    /**< 0x001C: DMM Direct Data Mode Destination Register                */
    uint32  DDMBL;      /**< 0x0020: DMM Direct Data Mode Blocksize Register           */
    uint32  DDMPT;      /**< 0x0024: DMM Direct Data Mode Pointer Register        */
    uint32  INTPT;      /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register     */
    uint32  DEST0REG1;  /**< 0x002C: DMM Destination 0 Region 1           */
    uint32  DEST0BL1;   /**< 0x0030: DMM Destination 0 Blocksize 1                     */
    uint32  DEST0REG2;  /**< 0x0034: DMM Destination 0 Region 2                  */
    uint32  DEST0BL2;   /**< 0x0038: DMM Destination 0 Blocksize 2                 */
    uint32  DEST1REG1;  /**< 0x003C: DMM Destination 1 Region 1                  */
    uint32  DEST1BL1;   /**< 0x0040: DMM Destination 1 Blocksize 1                 */
    uint32  DEST1REG2;  /**< 0x0044: DMM Destination 1 Region 2                   */
    uint32  DEST1BL2;   /**< 0x0048: DMM Destination 1 Blocksize 2                  */
    uint32  DEST2REG1;  /**< 0x004C: DMM Destination 2 Region 1                  */
    uint32  DEST2BL1;   /**< 0x0050: DMM Destination 2 Blocksize 1                  */
    uint32  DEST2REG2;  /**< 0x0054: DMM Destination 2 Region 2  */
    uint32  DEST2BL2;   /**< 0x0058: DMM Destination 2 Blocksize 2   */
    uint32  DEST3REG1;  /**< 0x005C: DMM Destination 3 Region 1 */
    uint32  DEST3BL1;   /**< 0x0060: DMM Destination 3 Blocksize 1                       */
    uint32  DEST3REG2;  /**< 0x0064: DMM Destination 3 Region 2              */
    uint32  DEST3BL2;   /**< 0x0068: DMM Destination 3 Blocksize 2              */
    uint32  PC0;        /**< 0x006C: DMM Pin Control 0                          */
    uint32  PC1;        /**< 0x0070: DMM Pin Control 1               */    
    uint32  PC2;        /**< 0x0074: DMM Pin Control 2              */
    uint32  PC3;        /**< 0x0078: DMM Pin Control 3              */
    uint32  PC4;        /**< 0x007C: DMM Pin Control 4   */
    uint32  PC5;        /**< 0x0080: DMM Pin Control 5                 */
    uint32  PC6;        /**< 0x0084: DMM Pin Control 6                              */
    uint32  PC7;        /**< 0x0088: DMM Pin Control 7                             */
    uint32  PC8;        /**< 0x008C: DMM Pin Control 8                              */

Regards
Prathap

Hello Prathap,

sorry, my post can be a bit confusing - there were mentioned an order of bits within a register. Halcogen generates someting like that:

/** - DMM Port direction */
dmmREG->PC1 = 1U /* DATA[0] */
| (1U << 1U) /* DATA[1] */
| (1U << 2U) /* DATA[2] */
| (1U << 3U) /* DATA[3] */
| (0U << 4U) /* DATA[4] */
| (1U << 5U) /* DATA[5] */
| (1U << 6U) /* DATA[6] */
| (0U << 7U) /* DATA[7] */
| (0U << 8U) /* DATA[8] */
| (1U << 9U) /* DATA[9] */
| (1U << 10U) /* DATA[10] */
| (1U << 11U) /* DATA[11] */
| (0U << 12U) /* DATA[12] */
| (1U << 13U) /* DATA[13] */
| (1U << 14U) /* DATA[14] */
| (1U << 15U) /* DATA[15] */
| (1U << 16U) /* DMM SYNC */
| (1U << 17U) /* DMM CLK */
| (1U << 18U); /* DMM ENA */

But I think that should be as follows:

Please ignore another form (type) - be focused on the bit order:

struct DMM_PIN_BITS
{
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
#else
 unsigned reserved : 13;
 unsigned ena : 1;
 unsigned data15 : 1;
 unsigned data14 : 1;
 unsigned data13 : 1;
 unsigned data12 : 1;
 unsigned data11 : 1;
 unsigned data10 : 1;
 unsigned data9 : 1;
 unsigned data8 : 1;
 unsigned data7 : 1;
 unsigned data6 : 1;
 unsigned data5 : 1;
 unsigned data4 : 1;
 unsigned data3 : 1;
 unsigned data2 : 1;
 unsigned data1 : 1;
 unsigned data0 : 1;
 unsigned clk : 1;
 unsigned sync : 1; /* 0-th bit */
#endif
};

Thanks,

Best regards, Jiri

Hi Prathap,

thank you and your Halcogen team for support and especially for bugfix implementation in the next release.

It is nice to have a correct file although not necessary ;-)

Best regards, Jiri