Other Parts Discussed in Thread: HALCOGEN
Hello, here is the code of HALCoGen, explain to me why every even mailbox is initialized through the registers IF2 and not even a mailbox IF1? What's the point? Yet it is not clear because each time you send and receive a new message comes povtoranya configuration registers IF1 as transmitters and IF2 for the reception. What's the point, for what it's done for each call canTransmit () and canGetData ()?
/** - Initialize message 1
* - Wait until IF1 is ready for use
* - Set message mask
* - Set message control word
* - Set message arbitration
* - Set IF1 control byte
* - Set IF1 message number
*/
while ((((canREG1->IF1CMD & 0x0000FF00U) >> 8U) & 0x00000080U) == 0x00000080U)
{
} /* Wait */
canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);
canREG1->IF1MCTL = 0x00001080U | 0x00000800U | 8U;
canREG1->IF1CMD = (canREG1->IF1CMD & 0xFF00FFFFU) | (0xF8U << 16U);
canREG1->IF1CMD = (canREG1->IF1CMD & 0xFFFFFF00U) | (1U);
/** - Initialize message 2
* - Wait until IF2 is ready for use
* - Set message mask
* - Set message control word
* - Set message arbitration
* - Set IF2 control byte
* - Set IF2 message number
*/
while ((((canREG1->IF2CMD & 0x0000FF00U) >> 8U) & 0x00000080U) == 0x00000080U)
{
} /* Wait */
canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
canREG1->IF2ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);
canREG1->IF2MCTL = 0x00001080U | 0x00000800U | 8U;
canREG1->IF2CMD = (canREG1->IF2CMD & 0xFF00FFFFU) | (0xF8U << 16U);
canREG1->IF2CMD = (canREG1->IF2CMD & 0xFFFFFF00U) | (2U);
/** - Initialize message 3
* - Wait until IF1 is ready for use
* - Set message mask
* - Set message control word
* - Set message arbitration
* - Set IF1 control byte
* - Set IF1 message number
*/
while ((((canREG1->IF1CMD & 0x0000FF00U) >> 8U) & 0x00000080U) == 0x00000080U)
{
} /* Wait */
canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);
canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
canREG1->IF1CMD = (canREG1->IF1CMD & 0xFF00FFFFU) | (0xF8U << 16U);
canREG1->IF1CMD = (canREG1->IF1CMD & 0xFFFFFF00U) | (3U);
