Is there a separate TCM Hard Error Cache [64-Bit] for ATCM, B0TCM and B1TCM?

Hi Pashan, 

 We have received your query. We will get back to you at the earliest possible

Regards,

Praveen

Pashan,

Depending on the type of access (DATA or FETCH) the CPU will react on hard error as DABORT or PABORT.

Your abort handlers will have to access Fault Status Registers (FSRs) and the Fault Address Register (FAR) for more information on the cause of the abort.

Hello Jean-Marc,

I am asking the following ITEM called TCM Hard Error Cache [HEC] as shown below from ARM TRM DDI0363e for Silicon Version r1p3.

Are they available as a separate 64-Bit Internal BUFFER for ATCM and BxTCM individually? Please confirm.

Thank you.
Regards
Pashan

Pashan,

This information is available in a standalone document that requires NDA. (PR284-PRDC-009908 0.6) I can't share it on the forum.

You can contact ARM and ask for this document. We can than push ARM to add this documentation part of the TRM.

Pashan,

Were you able to get this document from ARM?

Hello Jean-Marc,

ARM says that it supports only CUSTOMERs of ARM CORE IP.

Our company is not CUSTOMER and hence they don't have any technical support related to ARM.

We are supposed to ask the IC Vendor for all the information.

Let me know.

Thank you.
Regards
Pashan

Pashan,

I've send the documentation to your local FAE.

Please let me know when you get it.

Hi Pashan,

Unfortunately the confidentiality level set by ARM for this document does not allow TI to provide distribution.  We'll contact them and ask them to re-evaluate the confidentiality level for this document.

Regards,

Karl

Pashan,

What is the status on this question? Were you able to get the document? If so, can you please mark our response as verified answer so we can close this thread.

Hello Jean-Marc,

I am yet to get it.  I will ask FAE again.

Please wait. I will close the thread once I get the document.

Thank you.
Regards
Pashan

Hello Pashan,

I will wait on you to close it.