Please provide a DEMO of Imprecise Abort Example Project for Hercules

Pashan None

Genius 5660 points

Other Parts Discussed in Thread: TMS570LS3137, TMS570LS0432

Hello Support,

I tried the method as suggested by Jean-Marc in

http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/200399/715786.aspx#715786

for generating Imprecise Abort [ATYPE=1] in IMPFASTS Register.

I am unable to create Imprecise Abort even though I tried setting up MPU for CRC Peripheral Memory to DEVICE Type as CPSR A-Bit as ZERO.

While accesing CRC Base Address + 0x210 using LDR Instruction, I still get Precise Abort instead of Imprecise Abort.

Can you please provide a complete DEMO project with Imprecise Abort for Hercules [TMS570LS3137 or TMS570LS0432 device will be fine]?

Thank you.
Regards
Pashan

over 12 years ago

0 Zhaohong Zhang over 12 years ago

TI__Mastermind 22715 points

Pashan,

Imprecise abort is only applicable to writes. You can change the LDR instruction to an STR.

Thanks and regards,

Zhaohong

0 Pashan None over 12 years ago in reply to Zhaohong Zhang

Genius 5660 points

Hello Zhahong,

I had typo error in my original e-mail. I indeed performed STR instead of LDR.

It takes Precise Abort instead of Imprecise Abort.

Plesae help me soon with a small DEMO Project where ATYPE Bit is SET to HIGH within ABORT Handler.

Thank you.
Regards
Pashan

0 Zhaohong Zhang over 12 years ago in reply to Pashan None

TI__Mastermind 22715 points

Pashan,

Why do you consider it not a imprecise abort? You will not see the abort if you do not enable imprecise abort at CPSR.

Thanks and regards,

Zhaohong

0 Pashan None over 12 years ago in reply to Zhaohong Zhang

Genius 5660 points

Hello Zhahong,

Because when PC hits the ABORT Vector, I captured IMPFASTS register contents and I see ATYPE=0.

That's what I am trying to change to ATYPE=1.

Let me know.

Thank you.
Regards
Pashan

0 Zhaohong Zhang over 12 years ago in reply to Pashan None

TI__Mastermind 22715 points

Pashan,

(1) You need to clear "A" bit in CPSR register to enable imprecise abort.

(2) In the abort handler, you can check the Data Fault Status Register (DFSR) to see the cause of abort. See p4-57 of R4 TRM (ARM DDI 0363C) for more details.

Thanks and regards,

Zhaohong

0 Pashan None over 12 years ago in reply to Zhaohong Zhang

Genius 5660 points

Hello Zhaohong,

I am trying to observe IMPFASTS Register ATYPE Bit. Can you please confirm what should happen to ATYPE Bit of IMPFASTS Register under Imprecise Abort?

Thank you.
Regards
Pashan

0 Zhaohong Zhang over 12 years ago in reply to Pashan None

TI__Mastermind 22715 points

Pashan,

On Cortex R4, all behaviors are reported by Cortex R4. Many status registers in the TI system module are no longer applicable. Cortex R4's DFSR register is the only information source for the abort cause. IMPFASTS register is no longer applicable here.

Thanks and regards,

Zhaohong

Arm-based microcontrollers

Arm-based microcontrollers forum

Please provide a DEMO of Imprecise Abort Example Project for Hercules