Read in ADC RAM 1

Brice Plavonil

Other Parts Discussed in Thread: HALCOGEN

Hi,

on RM48x or TMS570LS dev board kit

I set the ADC to read in continuous mode, and set the ADC memory to be 64 on group1. Eventually I set the fifo size to 64 even if I can't figure out what is the link between the adc fifo and the group memory.

I start my conversion ...

and stop the conversion when fifo is full, assuming that the adc RAM contain the 64 values converted.

I realize that in the adc RAM there is more than 256 available values ? is it possible ?

because the TRM says that there are 64 buffers for conversion possible on the ADC,Somewhere else it says that there 1024 buffers ? where is the truth ?

the BNDB part in the ADBNDCR register says that it is possible to have 1FFh x 2 = 512 x 2 buffers ?

How could I know that I reached the accurate number of conversion that I want before reading the adc RAM ?

thank you beforehand.

Brice

over 12 years ago

0 Zhaohong Zhang over 12 years ago

TI__Mastermind 22715 points

Brice,

On the device, only 64 buffers are actually implemented although the design could be expanded for more buffers.

The following thread may provide useful information about how use ADC for continuous conversion.

http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/263949/926143.aspx#926143

Thanks and regards,

Zhaohong

0 Brice Plavonil over 12 years ago in reply to Zhaohong Zhang

Intellectual 720 points

Hi Zhaohong,

thank you for your reply, and for the link.

However do you think I can have a quick explanation for my question 1

and for the question 3 without using DMA.

Thank you.

0 Zhaohong Zhang over 12 years ago in reply to Brice Plavonil

TI__Mastermind 22715 points

Brice,

(1) There are only 64 buffers in ADC RAM.

(2) You can set up a ADC buffer threshold and enable buffer threshold interrupt. When the number of conversion data reaches the threshold, an interrupt is generated. Then you can read the data from one of the FIFO address. You do not need to worry about where it is saved in the ADC RAM. the threshold should be less than the buffer size to allow processing delay.

We normally recommend to use DMA because peripheral access is a performance bottleneck.

Thanks and regards,

Zhaohong

0 Brice Plavonil over 12 years ago in reply to Zhaohong Zhang

Intellectual 720 points

Hi Zhaohong,

Thank you,

I am maybe wrong in my process, but as I understood it so far this is what I have done to set up the DMA :

Below, I inserted this picture of the code. What I have got are 0X8001XXXX as values, the 1 is for the chanel 1 but the 8 mean the value of conversion is not good. Do you have an idea ?

0 Brice Plavonil over 12 years ago in reply to Brice Plavonil

Intellectual 720 points

sorry the picture does not appear

this is the sys_main and adc.c attached

7823.sys_main.c

4135.adc.c

best regards

0 Zhaohong Zhang over 12 years ago in reply to Brice Plavonil

TI__Mastermind 22715 points

Brice,

Your DMA config is wrong. The DMA transfer should be triggered by HW (ADC). Please read the code example in the link I provided as reference.

Thanks and regards,

Zhaohong

0 Brice Plavonil over 12 years ago in reply to Zhaohong Zhang

Intellectual 720 points

Hi Zhaohong,

Thanks you nows it is running like clockwork !

regards,

Brice

0 Brice Plavonil over 12 years ago in reply to Brice Plavonil

Intellectual 720 points

Hi Zhaohong,

I have another question :

I managed to run the DMA chanel 1 and request line 10 for ADC1 Group 1

and in the same time with chanel 2 and request line 11 for ADC1 Group2 as specified in the datasheet for the RM48X.

However, when I try the same, by a changing with the ADC2 Group 1 with request line 16 (or Group 2 with request line 17) as specified, it does not work --> I have got no value in my buffer.

In the ADC2 register I have got the G1DmaCtrl (or G2DmaCtrl) to 0X00200004 but it never decreases.

Is there a specifique thing I missed with the ADC2 ? do you confirm that the reqline is what said for the adc2 ?

Can you help me on that ?

Thank you,

Kind regards

Brice

0 Zhaohong Zhang over 12 years ago in reply to Brice Plavonil

TI__Mastermind 22715 points

Brice,

The ADC2 DMA request lines are correct. The values in the G1DmaCtrl/ G2DmaCtrl is also correct. I am suspecting if the ADC2 is running. You view the ADG1EMUBUFFER register in the CCS memory window to see if there are any valid data. You can also set up the ADG1THRINTCR/ADG2THRINTCR. The value in the G1THR/G2THR field should decreasing if conversion is happening.

Thanks and regards,

Zhaohong

0 Brice Plavonil over 12 years ago in reply to Zhaohong Zhang

Intellectual 720 points

Hi Zhaohong,

yes the conversion on ADC 2 is well started. I test it by getting the value directly in fifo.

With the same process on ADC2 there is an issue. it's weird.

I just set an RTI compare of 0.25 ms, but even when disabled, it not operate on the ADC2

Can I shared these files with you ?

Thank you,

Best regards

Brice

0 Zhaohong Zhang over 12 years ago in reply to Brice Plavonil

TI__Mastermind 22715 points

Brice,

Sure.

Thanks and regards,

Zhaohong

0 Brice Plavonil over 12 years ago in reply to Zhaohong Zhang

Intellectual 720 points

Zhaohong,

this is a zip file of a little project.

The main files are :

ADC_DMA_Configuration.c --> which configure the channel, the request line, the packet for the dma device, and the Read (adc fifo) and Write (my data buffer) destination

adc.c --> I created the adcStartConversionX that set up the G1DMA or G2DMA block to 32 values, and then start the conversion on the selected adc channel

0451.AdcTimingSimple2.zip

thank you

regards,

Brice

0 Brice Plavonil over 12 years ago in reply to Brice Plavonil

Intellectual 720 points

Hi Zhaohong,

I just realize that Halcogen did not generate properly the init function for adcReg2 !

This is bizare. I made the correction and it work fine now !!!

I don't know why Halcogen had this behaviour, I tried to re-generate and it still don't create a proper adcInit function.

maybe you can try to re-generate from you side, if you see the adcReg2 initialisation in the adcInit function. It could be a Halcogen bug.

the version is V03.05.02

Thank you for your time.

Brice

0 Zhaohong Zhang over 12 years ago in reply to Brice Plavonil

TI__Mastermind 22715 points

Brice,

Thanks for the update. I have forwarded your finding to the HALCoGen team.

Thanks again for your support.

Zhaohong

0 Prathap over 12 years ago in reply to Brice Plavonil

TI__Genius 14205 points

Hi Brice,

I am sorry I could not get the full issue, Could you please share the original adc file and the fixed one to help us analyze the issue.

Could you please share the complete project or atleast the HALCoGen project files ( .hcg and .DIL).

Regards
Prathap

0 Brice Plavonil over 12 years ago in reply to Prathap

Intellectual 720 points

Hi Prathap,

I am afraid, I am just realising that the ADC 2 was not ticked properly in Halcogen, this is what explains the no-generation of the initialising of ADC2.

No bug so far in Halocgen.

Thank you,

Brice

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Read in ADC RAM 1