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Question about pinmux for 4 certain pins

Tom Major
Intellectual 260 points

Hello,

I am currently designing a board with a TMS5703137BZWTQQ1 and have to look at each pin for all my desired functions.

For these 4 pin functions, two ball grid pins are assigned (document SPNS162A –APRIL 2012–REVISED NOVEMBER 2012)

HET1_21:  H4 J3
HET1_27:  A9 B2
HET1_29:  A3 C3
GIOB_2:  F2 V10

Is this some kind of error or is this correct? How can one have the same pin function (like GIOB_2) on two different pins? E.g. how can one read one GIO B2 input from two different pins?

Would be great if someone from TI could clarify this.

Thanks,

Tom

  • 0
    TI__Mastermind 49120 points

    Hello Tom,

    Let me describe the functionality separately for the N2HET1 and the GIO signals.

    The N2HET1 functions 17, 19, 21, 23, 25, 27, 29 and 31 have a dedicated ball as well as an alternate ball on which they appear as a multiplexed option. The application needs to configure specific I/O multiplexing control registers if these functions are required to be output from these alternate balls. Note that the dedicated balls will always carry the outputs, so you may end up getting the same function output on two balls.

    There is also a multiplexer on the input path to select between the dedicated ball (default) and the alternate ball. Again, this selection is controlled by registers in the I/O multiplexing control module.

    Since you have a dedicated terminal on the ZWT package, it was presumed that you won't need to use these functions on the alternate terminals. This functionality was specifically designed for the 144-pin QFP package which does not have dedicated terminals for these N2HET1 functions.

    Coming to the GIOB[2] function now. The GIOx terminals have the important feature of being able to trigger an interrupt to the CPU on a state change (programmable). GIOB[2] also has a dedicated terminal on the 337BGA (F2). The functions implemented on the terminal V10 are MIBSPI3NCS[0]/AD2EVT. There is also another function that is unfortunately not listed in the datasheet (will be corrected in the next release). This is the function called N2HET2_PIN_nDISABLE. This function can be used to disable PWM outputs from N2HET2 when the PIN_nDISABLE is driven low (see N2HET chapter in technical reference manual, SPNU499 for more details). This PIN_nDISABLE is usually driven by an external fault monitor, e.g. a motor over-current detection circuit.

    It is important for the CPU to get notified whenever the N2HETx PWM outputs are disabled. This is why we also provided a path from the N2HET2_PIN_nDISABLE input to the GIOB[2]. This input path needs to be enabled via the I/O multiplexing control registers as also described in the TRM.

    We are trying to explain the multiplexing functionality better in future updates to the TRM. Please let me know if this description helps.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 260 points

    Hello Sunil,

    thank you very much for your extensive und comprehensible answer. This answers my questions completly.

    I will use the dedicated balls for these HET1 functions and don't care about the alternate balls on the ZWT package.

    Thanks and regards,

    Tom