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RM48L952 max ADC sample speed

Jack Andrews
Intellectual 370 points
Other Parts Discussed in Thread: RM48L952, HALCOGEN

Hi, section 5.2.1 of the RM48L952 data sheet says: "Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK".  Does this mean it is possible to achieve ~1.6MSPS?  Also, HalCoGen seems to suggest that the ADC RAM is 64 words long... does this mean you can do up to 64 samples before reading out the results?  Finally, do you think it would be possible to achieve ~625kSMS continously at 10 bit resolution?  We are particularly interested in the phase of the signal so timing, especially between start new transfer groups, is important. Note also that I'm already pushing ~75Mbit/s through the DMA (SPI).

Thanks,

Jack

  • 0
    TI__Guru**** 196286 points

    Hi Jack,

    The ADC on the RM48x series has a 12bit (or 10bit, configurable)  resolution conversion unit.

    As per specification, the Max clock speed for the ADC is 30Mhz (Programmable via ADC Clock Prescaler)
    The minimum sample and hold time has to be 200ns. (programmable via Acquisition Prescaler Bits) 
    The minimum conversion time has to be 400ns (12 x 33.33ns)

    The formula to calculate the total minimum conversion time is:

    TTOT = TSAMPLE + TCONV = TVCLK * PS (ACQ + 10)

    Where:

    TSAMPLE   SAMPLING TIME
    TCONV       CONVERSION TIME
    T VCLK     PERIOD
    TTOT         TOTAL MEASUREMENT TIME
    PS            ADCLK PRESCALE SELECT (1 to 32)
    ACQ          ACQUISITION PRESCALE SELECT (2 to 4096)

    There are 4 VCLK cycles between the end of conversion of one channel and the start of conversion of the next channel within the same group. There are also other delays related to the ADC module design (2~3 cycles). There is another minor delay for storing data to RAM.

    With these number, the maximum ADC conversion rate is around 1.2M sample per second.


    Regards,

    QJ