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SSI Slave Mode Tx FIFO - How to empty the FIFO (Initialize prior to commencing uDMA)

Glenn Jones
Prodigy 150 points
Other Parts Discussed in Thread: TM4C1233H6PM, TM4C123GH6PM

I am using the SSI peripheral as an SPI Slave

I need to empty the Tx FIFO prior to beginning a uDMA transfer to a Master

There seems to be no way to clear the FIFO to a known state. This means that the FIFO may, or may not, have residual data in it that the SPI Master is not expecting

If the Master fails to read the entire transfer and initiates another it will receive stale data that remains in the FIFO.

If I switch to Slave mode to attempt to clear the FIFO the Clock signals are driven from both the Master and Slave (not good!)

Enabling / disabling the SSI peripheral has no effect. I see no way short of a power cycle to clear the FIFO.

I can detect it: SSICR1 = 0x06 (Slave / Enabled) SSISR = 0x10 ( Busy/Tx FIFO Full )

The receive FIFO can be cleared in either Master or Slave mode easily, the Tx FIFO in Master mode is continually emptied, but in Slave mode there is an issue!

 

May have answered my own question: The only way I have found to clear the FIFO is to Issue a software reset in the SRSSI register and reprogram the SSI peripheral. Seems like a crude solution. So my question still stands...

I need a way to empty the FIFO - help?

 

  • 0
    Guru 92251 points

    Glenn Jones said:
    There seems to be no way to clear the FIFO to a known state.

    Not sure which device you are using, but looking at the datahsheet for a TM4C1233H6PM agree that there is no register bit to clear the transmit FIFO.
    Glenn Jones said:
    Enabling / disabling the SSI peripheral has no effect. I see no way short of a power cycle to clear the FIFO.
    Does your device have a Synchronous Serial Interface Software Reset (SRSSI) or a Software Reset Control 1 (SRCR1) register?

    The software reset control allows individual SSI peripherals to be reset, which should hopefully clear any data left in the FIFOs (I haven't tried it myself).

    Glenn Jones said:
    If the Master fails to read the entire transfer and initiates another it will receive stale data that remains in the FIFO.
    For other microcontrollers, e.g. MSP430, I have seen the recomendation is to use software to reset the SSI peripheral after the chip-select has gone inactive (i.e. at the end of each transfer) to avoid such a failure.

  • 0 in reply to Chester Gillon
    Prodigy 150 points

    Thanks for the input.

    I am using a  TM4C123GH6PM.

    I can solve the problem using the SRSSI register (as you suggest) but this is not elegant at all and time consuming - I need to keep the SSI port running at 4 MHz.

    Was hoping for a more elegant solution - the part is otherwise quite remarkable - we use them in several applications.

     

  • 0
    Guru 117855 points

    Glenn Jones said:

    I need a way to empty the FIFO - help?

    And then - after responder generously attempts to assist: "...hoped for a more elegant solution!"

    Perhaps a more elegant request (so stipulating such hope) should have been issued...