Single Error Counter Threshold doesn't work as described in spnu517.pdf for F021 Flash Wrapper

Hi Pashan,

I will forward your question to our expert on F021 Flash. He will test and respond you soon. Thanks 

Regards,

QJ

Hello QJ,

Any news about my question related to F021 SINGLE_ERROR_COUNTER and THRESHOLD relation?

Thank you.
Regards
Pashan

Hi Pashan,

how do you create single bit error to trigger the flash controller to count?

Hello Henry,

Basically if you read ERASED Flash space then for Even 64-Bit address you will get Correctable Error as mentioned in this link :

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/269595.aspx

Thank you.
Regards
Pashan

Hi Pashan,

i zoomed in but can not see your register dump very clearly.

can you please let me know the register values for FEDACCTRL1?

Something does not make sense from the above thread btw.

Hello Henry,

I have attached the original JPEG as ZIP so that you can see in Windows.

In the other thread I asked the following :

  If you read every EVEN 64-Bit Address of Erased Flash Space, then you will get SEC Fault and for Odd 64Bit Address you will get DED ABORT.

Then Jean-Marc said that because of ADDRESS Lines in ECC Calculation anything can happen with Multi-Bit Error.

May be you can verify at your end with some test case and attach the whole TEST CASE Project here. That will help me a lot to find out the discrepancy.

Let me know if you need any more information.

Thank you.
Regards
Pashan

Pashan,

i would like to clarify a few things:

#1- when FEDACCTRL1[19:16] is set to 0x0 in your case, then, the flash controller will strip out the address component, and return the new ECC (no longer all 1s) + data (all 1s) to CPU.  Depending on your address value, you may or may not get single or "non-single" bit error or maybe no error.  it is not always fixed to EVEN address for single bit error and ODD address for non-single bit error.  So you will have to try 

#2- You need to set the FEDACCTRL1[8] to 1  (EPEN bit) to enable error profiling. 

can you please try #2 and let us know if this fixes your problem?

Hello Henry,

I am attaching the Debugger Screenshot with EPEN Bit SET.

Remember the original question about this current thread.

Question was how come SEC_CNT greater than SEC_THRESHOLD.

You asked how am I creating SEC FAULT in Flash Wrapper and hence I said about another e2e link.

In the attached ZIP file you will see that EPEN Bit is SET but still SEC_CNT is greater than SEC_THRESHOLD.

Let me know,

Thank you.
Regards
Pashan

Pashan,

I created a simple example and it works as the TRM mentioned with EPEN bit turned on.

The SEC_CNT got reset to 0 and i can see the program jumps to flash abort routine.

I can see ESM group 1 channel 6 got set.  

See this in the attached jpg.  I also attached the CCS project i used for this testing.

It is a very SIMPLE test.

Best Regards,

Henry Nguyen

1565.Forum Image Flash SECDED.zip

4760.Flash_SECDED_TEST.zip

Pashan,

let me describe what i did:

1- Erase the ENTIRE flash using CCS on-chip flash option

2- Select Necessary Sector Only in Erase option for loading + click on auto ECC  (do this step right before you load your program)

3- Add _coreEnableFlashEcc()_; function call in your sys_startup.c codes like below snap shot

/* USER CODE BEGIN (38) */
/* USER CODE END */

/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
_coreEnableRamEcc_();

/* USER CODE BEGIN (39) */

_coreEnableFlashEcc_();      // <<=== add this

/* USER CODE END */

Hello Henry,

Thank you for your demo code.
I have modified the following files :

1> setupPLL() in system.c for 8MHz XTAL and GCLK/HCLK as 40MHz  -- You might have to change the #if 0 to #if 01 for your CPU
2> fmcECCcheck(() in sys_selftest.c for monor correction related to clearing of Single Bit Error ADDRESS Read
3> sys_core.asm -- for removing the Floating Point Unit because I am using Corona Device TMS570LS0432
4> main() function in sys_main.c for Multiple Single Bit Error and OTP ECC Check

I have attached the Flash_SECDED_TEST_parity.hex file inside "Out" folder of ZIP file, which is created with nowECC 2.21.00 version.
Use Flash470.exe Tool to program the complete Flash Area with the Flash_SECDED_TEST_parity.hex after erasing the entire Flash.
Then Power Cycle the CPU without Debugger connected.
Then connect Debugger to dump the Flash Wrapper Address range 0xFFF87000 ---
You will see that SEC_CNT > SEC_THRESHOLD.
Let me know if you can't see the fault.
Thank you.
Regards
Pashan

Pashan,

Please take a look at the attachment.

I don't use flash tool.  I use CCS to erase entire flash, then, enable auto ECC to program only necessary sector section.

In the attachment, you can go to the main.  then, from main, you can start stepping the codes.

You can see that there is a single bit error (FEDACSTATUS[1]=1) then, the single bit error counter increments to 1 and then wrap back to 0 when the next (2nd) error occurred (i set the threshold = 2).  

2514.Flash_SECDED_TEST_July_15.zip

Hello Henry,

In your July15 Build you didn't use my sys_selftest.c file as attached before.

In your July15 Archive you didn't SWITCH ON EPEN Bit inside fmcBus2Check().
Once you switch on EPEN Bit inside fmcBus2Check() as shown below, you will get the ERROR I was mentioning.

Let me know if you still cannot get the fault. Please attach your software in case you can't get the fault.
Thank you.
Regards
Pashan

Hi Pashan,

i disagree with you on this point because i did enable EPEN bit again after fmcBus2Check(); in the main codes.

See my attached project again.  snippet of codes:

#define test_location_SEC_0 ((uint32 volatile *)0x000C008U)
#define test_location_SEC_1 ((uint32 volatile *)0x000E060U)
#define test_location_SEC_2 ((uint32 volatile *)0x000C068U)
#define test_location_SEC_3 ((uint32 volatile *)0x000C038U)
#define test_location_SEC_4 ((uint32 volatile *)0x000C058U)

uint32 volatile test_location_value ;
uint32 volatile temp;

fmcBus2Check();

flashWREG->FEDACCTRL1 = 0x010A070AU;   <<<<=============== reanble EPEN again here before proceeding to test single error bit counter 
flashWREG->FEDACCTRL2 = 0x00000002U;

test_location_value = *test_location_SEC_0;
//temp = flashWREG->FCORERRADD; /* Clear Error */

/* 1-bit failure was indicated and corrected */
flashWREG->FEDACSTATUS = 0x00010006U;

Hello Henry,

I did EPEN bit enabled inside fmcBus2Check() as the first line -- If you do that according to my attached sys_selftest.c you will get the error :

void fmcBus2Check(void)
{
/* USER CODE BEGIN (44) */
/* USER CODE END */
    /* enable ECC logic inside FMC */
//  flashWREG->FEDACCTRL1 = 0x000A060AU;
    flashWREG->FEDACCTRL1 = 0x010A070AU;

    if ((esmREG->ESTATUS1[0U] & 0x40U) == 0x40U)
    {

Let me know once you change the code inside fmcBus2Check() as the first line.

Thank you.
Regards
Pashan