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TMS370LS3137 Clock Questions

Hello,

1) What triggers a Clock Monitor Interrupt (ESM 1.11)?

2) If a PLL slip results in an automatic switchover to the oscillator, are the existing dividers for downstream clocks still in place?  I.e., will the downstream clocks be slowed down proportionately?

Thanks, Charlie Johnston

  • Hi Johnston,

    The LPO Clock Detect module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO). The LPO provides two different clock sources: CLK80K and CLK10M. The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL),  switches all clock domains sourced by OSCIN to the CLK10M clock, and generate the clock monitor interrupt (ESM1.11).

    Like the oscillator, the PLL clock is configured by default to automatically switch-over to the oscillator in case of a PLL slip. In this case, the oscillator sources GCM clock source 1 as well as GCM clock source 0. Also, if the oscillator fails, LPO HF is sourced to both GCM clock sources 0 and 1. The PLL divider doesn't change.

    Regards,

    QJ

  • Hi QJ,

    That's exactly what I was looking for.

    Thanks for your quick reply.

    Charlie Johnston