ESM Group 1 Status Register Update independent of ESM Group 1 Interrupt or Error Pin

Pashan None

Hello Support,

In the ESM, does Group 1 Status Register is updated with error flags independent of settings of ESM Group 1 Effect on ERROR Pin or Interrupt Enable?

That means when ESMDEPAPR1 = 0xFFFF_FFFF and ESMIECR1 = 0xFFFF_FFFF, does for any valid ESM Group 1 Error condition the ESMSR1 register will be updated with respective ERROR Flags?

Thank you.
Regards
Pashan

over 12 years ago

0 Anthony F. Seely over 12 years ago

TI__Guru 68920 points

Hi Pashan,

I looked through our internal docs and didn't see this clearly answered. Normally yes the status flag comes before the mask/enable so the status would be set for the event even if the interrupt is masked. But this IP looks potentially different. We're checking and will get back to you.

BTW you have a very sharp eye and your feedback is appreciated.

Best Regards,

Anthony

0 Henry Nguyen over 12 years ago in reply to Anthony F. Seely

TI__Expert 4225 points

Hi Pashan,

what you said is correct that the status bit will get captured regardless whether the interrupt enable for that status bit is active or not.

This is consistent with other status bit in other IP.

0 Pashan None over 12 years ago in reply to Henry Nguyen

Genius 5660 points

Hello Henry,

Status bit will get captured also independent of ERROR Pin Effect is enabled or not for ESM GROUP 1.

Is the above statement also correct?

I am assuming ERROR Pin Effect and Interrupt Enable for ESM Group 1 are independent gate function.

Please confirm.

Thank you.
Regards
Pashan

0 QJ Wang over 12 years ago

TI__Guru**** 196306 points

Hi Pashan,

The ESMSR1 is independent on the settings on ESMEEPAPR1 and ESMESR1. If ESMDEPAPR1=0xFFFFFFFF and ESMECR1=0xFFFFFFFF, when clock fails, the ESMSR1 will be set to 0x00000B00, but the ESMOFFHR or LR will not show any INT.

regards,

0 QJ Wang over 12 years ago in reply to QJ Wang

TI__Guru**** 196306 points

I tested by removing the OSC 16MHz clock input.

Regards,

0 Henry Nguyen over 12 years ago in reply to Pashan None

TI__Expert 4225 points

Hi Parsan,

yes, the status captured independent of the ERROR pin effect or not for group 1.

0 Pashan None over 12 years ago in reply to Henry Nguyen

Genius 5660 points

Hello Henry,

Can I assume that all the above mentioned behaviour is also TRUE for ESMSR4 Register [which is extended Group 1 Error]?

Thank you.
Regards
Pashan

0 Henry Nguyen over 12 years ago in reply to Pashan None

TI__Expert 4225 points

Hi Pashan,

yes, that is correct. i also confirmed that by looking at the design database.

Arm-based microcontrollers

Arm-based microcontrollers forum

ESM Group 1 Status Register Update independent of ESM Group 1 Interrupt or Error Pin