SPI0 as slave with DMA

Massimiliano Cialdi

Expert 1995 points

Other Parts Discussed in Thread: TM4C1231H6PGE

Hallo,

I have TM4C1231H6PGE and tivaware 1.0.

I need SSI0 to be slave, and I want to use DMA to transfer.

I attach a slice of code I use to setup SSI0 and DMA. When I try to run only first character seems to be read.

For example if the string "DATA\n\r" is sent by master (verified with logic analizer), in data[] array I find "DDDDDDD" (w/o '\0' termination).

where am I wrong? How an interrupt can be triggered at the end of transfer? How can I know if a transfer is in progress?

best regards

over 13 years ago

0 Bradley Higgin over 12 years ago

Intellectual 535 points

Your RX DMA is likely timing out due to the fact there isn't any data available yet. You should probably trigger your DMA from RX FIFO full interrupt, or if your SPI transfer size is <=8, trigger off of CS.

0 Amit Ashara over 12 years ago in reply to Bradley Higgin

TI__Guru**** 244450 points

Hi,

I think you are checking the address of data[0]. Can you check the varaibles data[1]... You would see the rest of the bytes.

For knowing the end of transfer you have to read the UDMA Interrupt Status Register. When the UDMA completes the transfer then the bit corresponding to the channel number will be set.

Regards

Amit

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SPI0 as slave with DMA