Other Parts Discussed in Thread: TM4C1231H6PGE
Hallo,
I have TM4C1231H6PGE and tivaware 1.0.
I use SPI0 as slave. Master set SPI clock to 19200. I wonder what value set in
ROM_SSIConfigSetExpClk(SSI0_BASE, 24576000UL, SSI_FRF_MOTO_MODE_0, SSI_MODE_SLAVE, 192000, 8);
Keep in mind that core master clock is 24.576 MHz (PLL is bypassed).
I have tried 3 different values: 19.2 KHz, 192 KHz and 4.096 MHz.
when I set 192KHz the receive interrupt is triggered after about 165 us from last sclk edge (note that 165 us is about 32 times clock period @192KHz):
despite this, only one character is poped from FIFO, as if there were only one.
If I set 19.2KHz or 4.096MHz the interrupt is triggered after first character and no other interrupt are triggered:
Where am I worng? What are the clock speed limits for my configuration? How to calculate them?
I have attached the slice of code I use.
best regards