In reg_spi.h created by HalCoGen 03.05.02 for SPI 1-5 (TMS570LS1227ZWT) in structure spiBASE_t there are no DMA registers: DMACTRL, DMACOUNT, DMACNTLEN:
typedef volatile struct spiBase
{
uint32 GCR0; /**< 0x0000: Global Control 0 */
uint32 GCR1; /**< 0x0004: Global Control 1 */
uint32 INT0; /**< 0x0008: Interrupt Register */
uint32 LVL; /**< 0x000C: Interrupt Level */
uint32 FLG; /**< 0x0010: Interrupt flags */
uint32 PCFUN; /**< 0x0014: Function Pin Enable */
uint32 PCDIR; /**< 0x0018: Pin Direction */
uint32 PCDIN; /**< 0x001C: Pin Input Latch */
uint32 PCDOUT; /**< 0x0020: Pin Output Latch */
uint32 PCSET; /**< 0x0024: Output Pin Set */
uint32 PCCLR; /**< 0x0028: Output Pin Clr */
uint32 PCPDR; /**< 0x002C: Open Drain Output Enable */
uint32 PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
uint32 PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
uint32 DAT0; /**< 0x0038: Transmit Data */
uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
uint32 BUF; /**< 0x0040: Receive Buffer */
uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
uint32 DELAY; /**< 0x0048: Delays */
uint32 CSDEF; /**< 0x004C: Default Chip Select */
uint32 FMT0; /**< 0x0050: Data Format 0 */
uint32 FMT1; /**< 0x0054: Data Format 1 */
uint32 FMT2; /**< 0x0058: Data Format 2 */
uint32 FMT3; /**< 0x005C: Data Format 3 */
uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
uint32 SRSEL; /**< 0x0068: Slew Rate Select */
uint32 RESERVED[50U]; /**< 0x006C to 0x0130: Reserved */
uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
} spiBASE_t;
In IAR ARM 6.60 simulator on tab Register SPI 2, 4 structure of registers differs from spiBASE_t since FMT. But in IAR are available DMA registers DMACTRL, DMACOUNT, DMACNTLEN
Answer please:
1) Whether is DMA in SPI 1-5 in TMS570LS12x11? How actually looks spiBASE_t?
2) Where it is possible to look the correct bit-by-bit description of registers SPI 1-5
