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Please provide information about OTP contents for TMS570LS0432 device

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS0432

Hello Support,

In the OTP for TMS570LS0432 there are device related BUILD CONFIGURATION information.

Can you please provide the document which describes all the meaning of bit fields as present within TMS570LS0432 like MEMORY SIZE and BANK Information?

Also any other pertinent information.

In short, is there a document which describes REV or MASK Version and all other OTP content details as programmed by TI during manufactcuring?

That will be a great help.

Thank you.
Regards
Pashan

  • 0
    TI__Guru**** 193266 points

    Hi Pashan,

    I have forwarded your question to our Flash/OTP expert. He will contact you soon. 

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Genius 5660 points

    Hello QJ,

    Please help me with the requested information for OTP contents as present in TMS570LS0432 device.

    Thank you.
    Regards
    Pashan

  • 0
    TI__Genius 9015 points

    Hello Pashan,

    Only certain OTP locations are described and those descriptions may be found in the latest version of the device TRM.

    Some of the OTP information is parsed and returned by the F021 Flash API functions Fapi_getDeviceInfo() and Fapi_getBankSectors().

    The rest of the locations are considered reserved with no description available.

  • 0 in reply to John Hall
    Genius 5660 points

    Hello John,

    I couldn't find in spnu517a.pdf Section 4.4.2 OTP Memory any information about ECC Self-Checking locations with Double Bit and Single Bit Fault for Bank 0 and Bank 7.

    Please let me know which page of spnu517a.pdf I should look for that information.

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Genius 9015 points

    Hello Pashan,

    The best I can tell, that information is not listed in the TRM.  I will have to get back to you if it happens to be documented in another document.

  • 0 in reply to John Hall
    TI__Genius 9015 points

    Hello Pashan,

    The ECC Self-Checking locations with Double Bit and Single Bit Fault for Bank 0 and Bank 7 are not in any released documentation.  We will evaluate whether or not to add this information to a future revision of the device TRM.