Hi,
I'm working with a TMDX570LS31HDK and trying to implement a DMA transfer driven by RTI. The goal (for now) is to see the DMA transferring data from a buffer (TX_DATA in the code) to a single 8 bit location. The trnsfer should be 1 byte a time and should continue indefinetly (so should cycle TX_DATA ).
Here's my sysmain. Note: the Halcogen setup should be right because I see a debug message from the RTI IRQ function (not reported here)
#define D_SIZE 512
uint8 TX_DATA[D_SIZE]; /* DMA source buffer */
g_dmaCTRL g_dmaCTRLPKT;
sciInit();
rtiInit();
rtiEnableNotification(rtiNOTIFICATION_COMPARE0);
/* write some value on the source buffer just to see if something changes */
int i;
for (i=0;i<D_SIZE;i++){
if (i%2==0) TX_DATA[i]=0x00;
else TX_DATA[i]=0xff;
}
uint8 DMA_dest; /* DMA destination */
/* - assigning dma request: channel-0 with request line 12, should be the RTI, right? */
dmaReqAssign(0,12);
/* - configuring dma control packets */
g_dmaCTRLPKT.SADD = (uint32)&TX_DATA; /* source address */
g_dmaCTRLPKT.DADD = (uint32)&DMA_dest; /* destination address */
g_dmaCTRLPKT.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT.FRCNT = 1; /* frame count */
g_dmaCTRLPKT.ELCNT = D_SIZE; /* element count */
//g_dmaCTRLPKT.ELDOFFSET = 0; /* element destination offset - is required? */
// g_dmaCTRLPKT.ELSOFFSET = 0; /* element source offset - is required? */
//g_dmaCTRLPKT.FRDOFFSET = 0; /* frame detination offset - is required? */
//g_dmaCTRLPKT.FRSOFFSET = 0; /* frame source offset - is required? */
g_dmaCTRLPKT.PORTASGN = 4; /* port b */
g_dmaCTRLPKT.RDSIZE = ACCESS_8_BIT; /* read size */
g_dmaCTRLPKT.WRSIZE = ACCESS_8_BIT; /* write size */
g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT.ADDMODEWR = ADDR_FIXED; /* address mode write */
g_dmaCTRLPKT.AUTOINIT = AUTOINIT_ON; /* autoinit (loop) */
//g_dmaCTRLPKT.COMBO; /* I don't think is required, right? */
/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH0, DMA_HW);
rtiREG1-> SETINT = (0x01U << 8);
_enable_IRQ();
rtiStartCounter(rtiCOUNTER_BLOCK0);
/* the loop here is just to test is something changes in the destination */
uint8 DMA_compare=DMA_dest;
while(1){
if (DMA_compare!=DMA_dest){
sciDisplayText("dest changed",sizeof("dest changed"));
DMA_compare=DMA_dest;
}
}
Is there's some errors? (fore sure: it doesn't works!)
Thank you,
Matteo
