There is a FPGA connected with TMS570LS20216 in my design. I want to use the FPGA to program the internal flash of TMS570LS20216. Is it possible to do this?
By the way, is the JTAG interface the only one to program the internal flash?
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There is a FPGA connected with TMS570LS20216 in my design. I want to use the FPGA to program the internal flash of TMS570LS20216. Is it possible to do this?
By the way, is the JTAG interface the only one to program the internal flash?
You cannot program the Flash directly from the JTAG port (and JTAG is the only way to access the device to program it initially). You have to write code that uses the Platform F035 Flash API, download it to RAM and execute it.
One option for what you want to do, is pre-program a bootloader into the TMS570LS20216 that implements Flash programming interface.
It is the first time I use TMS570LS20216, so I still have several questions about the internal flash:
1 TMS570LS20216 must boot from the internal flash, is that right? Can I use an external EEPROM or PROM instead of internal flash to boot?
2 For the option of a pre-programmed bootloader for my design, I should write the code of bootloader and program this bootloader into the internal flash of TMS570LS20216. Then the FPGA can program the flash through JTAG interface by communicating with the bootloader. Is that right?
3 It seems there is another way to program the flash in my design. I write code that uses the Platform F035 Flash API and store it in the external PROM of FPGA. FPGA reads out the code from the PROM and downloads it to the internal RAM of TMS570LS20216. Then FPGA can control the programming through JTAG interface by communicating with the downloaded code in the RAM. Is that right?
1) It can only boot from internal Flash.
2) On item 2, you could connect any type of communication protocol to talk with the bootloader already programmed. You are not limited to JTAG.
3) This would also be a viable option.
If I want to download the code that uses the Platform F035 Flash API into the internal RAM, I have to know the protocol about the JTAG interface of TMS570LS20216. Where can I find the protocol about communicating with TMS570LS20216 through its JTAG interface? I want to evaluate if the FPGA has enough resources to do this work.
The ARM JTAG protocol is available from ARM.
Some basic details on ICEPICK can be found here: http://processors.wiki.ti.com/index.php/ICEPICK and in particular in this file: http://processors.wiki.ti.com/images/3/3c/Router_Scan_Sequence.pdf