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Reading from OTP Space as Byte is producing Double Bit as well as Single Bit Error

Pashan None
Genius 5660 points


Hello Support,

Performing BYTE Read using LDRB instruction from 0xF00C007FU is producing ESM Group 1 Bit 6 as well as ESM Group 3 Bit 7 ERROR.
It was mentioned that 0xF00803F8U contains 2-Bit Error programmed at factory as shown in the following link: http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/235956/828249.aspx#828249
I was expecting only Double Bit Error when reading the ECC Byte as shown above from TRM. But I am getting Single Bit Error as well.
Can you please tell me why both errors are occuring?
Thank you.
Regards
Pashan

 

  • 0
    TI__Mastermind 22715 points

    Pashan,

    We will start an investigation on the issue you reported. We will keep you updated about the progress.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    TI__Guru 69050 points

    Pashan,

    Bob Crosby is running this down.  Working theory is that the 72-bit wide OTP is being read & checked (hence both single and double bit error locations are actually read) but the error signals back are not being 'gated' by the byte lanes that the CPU is actually reading.   If this is the case, expect an errata.

    There is a simulation that has been requested to confirm the theory.  Please continue to be patient,  the simulation won't take long but getting someone to work on it might take a week or two due to queue time.

    Best Regards,

    Anthony

  • 0 in reply to Anthony F. Seely
    Genius 5660 points

    Hello Support,

    Any news about this issue?

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Guru 69050 points

    Pashan,

    Last update I got on this item was on 9/20,  when the status was that simulations had reproduced the issue on ECC reads but not data reads, whereas bench testing seemed to indicate data reads also had the problem.  So next step was to re-check on the bench.   Don't know if this has been done yet or not.

     

  • 0 in reply to Anthony F. Seely
    TI__Guru 59540 points

    Hello Pashan,

    I have confirmed the behavior you describe. The alternate method to prevent the single bit error from being flagged is to read the 64bit data at addres 0xF00803F8  instead of reading the ECC value.

    The issue is that when reading the data or the ECC byte, the adjacent location ad 0xF00803F0 is also read. This location contains a single bit error. However, during a data read, the single bit error is masked since it is not the targeted data read. During a read of the ECC byte, both locations are also read but the single bit error is not masked.

    The TRM description will be updated to indicate the different behvaior when reading the ECC byte versus reading the data.

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points

    Pashan,

    I also wanted to correct an earlier post that mentions a 72bit wide read. The OTP address you are reading is from the Bank0 OTP which is a 144bit wide bank so the full 144bits are loaded onto the bus.