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Does STRD Instruction writes 64-Bit to CRC Register?

Pashan None
Genius 5660 points

Other Parts Discussed in Thread: TMS570LS0432

Hello Support,

CRC Register is at Strongly Ordered Default Memory MAP according to DDI0363 ARM TRM because the base addres of CRC is at 0xFE00_0000.

Now in the e2e link as shown below in the snapshot : http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/192363.aspx?pi239031349=1It

It is mentioned there that for Strongly Ordered Memory will always have 32-Bit write even for STRD Instruction as shown below.

But in the e2e link as shown below : http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/269524/944668.aspx#944668

It is mentioned the opposite for STRD to write 64-Bit DATA for CRC as shown below.

May be my understanding is wrong. Please clarify with some more information about STRD instruction based 64-Bit writing to CRC Register wither with MPU enabled or not.

Thank you.
Regards
Pashan

  • 0
    TI__Mastermind 22715 points

    Pashan,

    What it means is that the access to the actual memory is broken into 32 bit accesses at the memory boundary even though CPU issues LDRD or STRD instructions. In hose cases, there will be two 32 bit access to memory. For a user, it is still a 64 bit access.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 5660 points

    Hello Zhahong,

    For the CRC Engine it always calculates 64-Bit DATA Stream for every Logical Write Strobe to CRC Register.

    So, if STRD is performing two 32-Bit WRITE STROBE to CRC Engine, then effectively CRC Engine will perform calculation on 128-Bit of DATA Stream with MSB of one Write Strobe and LSB of another Write Strobe as ZERO.

    Hence for our offline calculation of CRC value we need to accomodate that.

    So, the original question came up.

    Does STRD to CRC Engine per Write Cycle is internally 2 Write Strobe for CRC Engine or single Write Strobe of 64-Bit.
    Final CRC value depends upon how many Write Cycle is seen by CRC Engine.

    I am attaching one page for spnu480b.pdf for you to understand the real issue. In older ARM7 based Wega devices, this was always two WRITE Strobe of 32-Bit for every 64-Bit WRITE [STMIA Instruction] to CRC Engine. Question is does it happen also in TMS570 Cortex with STRD Instruction?

    Let me know.
    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Genius 13810 points

    I think this post answered your question:

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/281553.aspx

    make it simple: strd performs 64 write to CRC module.

    Regards,

    Haixiao

     

  • 0 in reply to Haixiao Weng
    Genius 5660 points

    Hello Haixiao,

    Thank you for the Demo.

    I have only one issue.

    Because STRD is not generated by TI ARM C Compiler in any way for ARM Mode, will STMIA in THUMB Mode will also perform 64-Bit Write to CRC Register independent of MPU programmed in Strongly Ordered or Device?

    C Compiler generates STMIA for THUMB Mode and STM instead of STRD instruction for ARM Mode.

    Usually we compile all source files in THUMB Mode. For TMS570LS0432 there is no DMA.

    Please let me know.
    It will be great if there is some explanation about when it is 32-Bit and when it is 64-Bit write from CPU even though STM or STMIA is being used.
    Thank you.
    Regards
    Pashan

  • 0 in reply to Haixiao Weng
    TI__Mastermind 22715 points

    Pashan,

    I have several discussions with our designers on this topic because the bench validation test also show different CRC signatures for the same pattern when writing in 64 bit and 32 bit modes. What explained to me is that for a burst write (STRD or STM), although the data out of CPU is 32 bit, the bridge then merges 2 32 bit data into one 64 bit data. Therefore, if you do a STRD or STM to CRC data register, the actual write is 64 bit.

    Thanks and regards,

    Zhaohong