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EMIF addressbus for async IO

Markus Uhle
Prodigy 190 points
Other Parts Discussed in Thread: HALCOGEN

Hi,

we have attached a FPGA to the external address bus of a RM46 controller.

We attached nCS[2,3,4] as chipselects, BA[0,1], A[0..12] as address bus and D[0..15] as databus.

We configured the memory protection unit to allow memory access to ASYNC1..4 via 16bit access.

We configured HalCoGen to enable ASYNC external access via nCS[2..4] via 16bit access.

We can see the correct nCS and nRD/nWR timing via oscilloscope on the external bus.

In a first test, we simply map all address-pins (A12..A0, BA1..BA0) to the Databus to see where the access takes place.

On different boards we see the following address.bits toggeling (and NOT toggeling):

Bit0..3 [= BA0, BA1, A0, A1]: always zero

Bit4..7 [=A2..5]: ok

Bit8..10 [=A6..8]: always zero

Bit11..14 [=A9..12]: ok

When using adresses greater than (nCS-OFFSET + 0x7fff), the memory protection unit throws a dabort.

What can I do to get correct addresses on the external addressbus?

  • 0
    TI__Mastermind 22715 points

    Markus,

    There is a mistake in your address connection. Please see the following block diagram from TRM.

    Please see more details in TRM.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    TI__Mastermind 22715 points

    Markus,

    You also need to check pinmux settings. You use the following as reference.

    --------------------------------------------------------------------- */
    /*    Configure the IOMM for EMIF pins                                        */
    /* --------------------------------------------------------------------- */
    /*Unlock the IOMM Register*/
        *(int *) 0xFFFFEA38  = 0x83E70B13;
        *(int *) 0xFFFFEA3C  = 0x95A4F1E0;
    /*Configure the IOMM Register*/
        *(int *) 0xFFFFFFA0  |= 0x80000000;
        *(int *) 0xFFFFEB14  = 0x02020101;//P1  //EMIF_DATA[5],EMIF_DATA[4]
        *(int *) 0xFFFFEB18  = 0x01010201;//P2  //EMIF_DATA[6]
        *(int *) 0xFFFFEB1C  = 0x02010102;//P3  //EMIF_DATA[8],EMIF_DATA[7]
        *(int *) 0xFFFFEB20  = 0x01010201;//P4  //EMIF_DATA[9]
        *(int *) 0xFFFFEB24  = 0x02010101;//P5  //EMIF_DATA[10]
        *(int *) 0xFFFFEB28  = 0x02010201;//P6  //EMIF_DATA[12],EMIF_DATA[11]
        *(int *) 0xFFFFEB2C  = 0x02010102;//P7  //EMIF_DATA[14],EMIF_DATA[13]
        *(int *) 0xFFFFEB30  = 0x02010101;//P8  //EMIF_DATA[15]
        *(int *) 0xFFFFEB38  = 0x02010201;//P10 //EMIF_DATA[2],EMIF_DATA[3]
        *(int *) 0xFFFFEB3C  = 0x01020101;//P11 //EMIF_DATA[1]
        *(int *) 0xFFFFEB40  = 0x01010201;//P12 //EMIF_DATA[0]
    //    *(int *) 0xFFFFEB48  = 0x01020101;//P14 // EMIF_RNW Read not Write
        *(int *) 0xFFFFEB50  = 0x02010102;//P16 //EMIF_nOE,EMIF_BA[0]
        *(int *) 0xFFFFEB54  = 0x02010201;//P17 //EMIF_ADDR[5],EMIF_nDQM[1]
        *(int *) 0xFFFFEB5C  = 0x02020102;//P19 //EMIF_ADDR[3],EMIF_nDQM[0],EMIF_ADDR[4]
        *(int *) 0xFFFFEB68  = 0x02010101;//P22    //EMIF_ADDR[2]
        *(int *) 0xFFFFEB84  = 0x01010001;//P29    //EMIF_CLK

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Prodigy 190 points

    Hi,

    we just figured out, what is the mistake:

    Set Bit 31 in GPREG1

    systemREG1->GPREG1 |= (1U << 31);

    There is ***NO HINT** in the technical manual. These bits are defined as "Reserved"

    There is a *** VERY VERY SMALL HINT *** in a foot note in the datasheet.

    It seems, that HalCoGen is not setting this bit, if the EMIF-interface is used.

    Please consider to update the technical manual and the HalCoGen.

  • 0 in reply to Markus Uhle
    Intellectual 765 points

    Hi,

    is there a way to 'activate' the pins which are necessary for EMIF in HalCoGen?

    I want HalCoGen to execute this:

    (systemREG1->GPREG1 |= (1U << 31);)

    Best regards,

    Andy

  • 0 in reply to Andy Kay
    TI__Mastermind 22715 points

    Andy,

    The source code generated by HALCoGen is only for very basic operations. You can always add instructions to the source code generated by HALCoGen for your specific need.

    Thanks and regards,

    Zhaohong