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EK-TM4C123GXL Schematic Question

Hello, I have a question regarding the Tiva C Launch Pad Eval Kit schematic. On page 3 you have PD6, PF1, and PF2 connected to I/O pins. You then have ports PA2, PA3, and PA4 connected to the DEBUG/VCOM Bus that is the JTAG interface to the main MCU. My question is what are the actual pin needed to connect to the MAIN MCU to support the ICDI? What are ports PD6, PF1, and PF2 used for since they are named the same as PA2-PA4? Any insight would be greatly appreciated. Thank you,

Rob

  • Rob Greenewald said:
    On page 3 you have PD6, PF

    Hi more details needed... Which file are you referring?

     ICDI connect two way, JTAG or SWD, if SWD is in place no JTAG pin are needed.

  • Hello Roberto, the file that I am referring to is spmu296.pdf. It is titled as "Tiva™ C Series TM4C123G LaunchPad Evaluation Board User's Guide" The schematic starts on page 19. I have also attached the document.

    7848.spmu296.pdf

    Rob

  • Roberto Romano said:
    if SWD is in place no JTAG pins are needed.

    Respectfully disagree - our findings: PC0-PC3 usually serve JTAG role (unless unlocked/reconfigured) on Stellaris/rebrand.

    PC0 & PC1 serve SWD.  While they are no longer JTAG - their SWD (clock/data) role remains and these two pins are indeed needed...

    The MCU serving as icdi uses pins chosen by icdi designer(s) to deliver the  JTAG protocol to the Target MCU's PC0-PC3 JTAG pins.

    Even after 15 years use of JTAG - schematic you neatly supplied - is not "xtal-clear" to this reporter.  Suspect that U2A's pins: PA2,3,4,5 carry the JTAG data to your Target. 

    Mystery to me is those 3 other pins (PD6, PF1, PF2) also w/ JTAG labels - but shown as inputs (my sense) upon this schematic.  I fail to see how JTAG signals - delivered to these "3 non-JTAG" MCU pins - serve much purpose...  (although - it is possible these are JTAG outputs - but in quick scan of your pdf - such did not "jump out.")

    Must confess - after 2nd read your post - my question is exactly yours!  (i.e. what's up w/PD6, PF1,2?)  

    Suppose if time & scope are handy - you could monitor for "sync" between the PA group and like named PD/PF pins.  I see little (i.e. NO) chance that these 3 (right side of schematic pins) serve as JTAG inputs...  And - may be, "copy/paste" gone wild...  (as concerns their JTAG labeling)

  • In this case a bit of insight from the designer is required.  We did not anticipate such dedicated study of the debug circuit and thus did not document as well as we could have.

    The current ICDI software uses only the port A pins for JTAG communications.  These were all placed on port A to make "bit banging" the JTAG lines simpler for the software.

    SWO/SWD is not currently supported by the ICDI firmware.

    The Port D and Port F pins are attached to JTAG communications lines to provide potential future support for hardware enhanced JTAG and SWO/SWD functions.  SWO/SWD is rather UART like.  JTAG we believe could be enhanced by using two SSI ports in tandem.  The pins on the right side of the schematic can provide SSI and UART hardware to the JTAG interface if it is later desired by the software team. These pins are not currently used but are reserved should we choose to use them in future firmware.

    So far we have found the ICDI firmware performance comparable to our older FTDI based solution.  We feel it adequately fills the role of an in-circuit debug.  

    Dexter

  • @Dexter -

    As usual, "Camp Dexter" to the rescue!  Thanks for this.  (record reveals this reporter - not far off-mark...)

    Might quick/easy improvement result from asterisk and "possible future JTAG/SWD use" - placed adjacent to "offending" Port D, F pins - upon schematic?

  • Thank you Dexter! That is exactly what I was hoping to hear, and answers my question completely.

    Rob