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Hello Support,
Once the user triggers RAMTEST Register's TRIGGER Bit, it is automatically RESET once the Selftest is completed.
How many GCLK Clock Cycles is the duration after which TRIGGER Bit is automatically RESET from SET state?
Please help,
Thank you.
Regards
Pashan
Pashan,
We are looking into this and will get back to you
Hercules forum support
IPashan
t takes 1 HCLK cycle for this bit to get RESET from SET state
So if CPU tries to read this bit, it’ll always read as ‘0’.
Hercules forum support