CRC algorithm for 20216 CRC module

I split the thread because the old thread has been closed.

Yes, they have the same CRC module.

The CRC algorithm can be found in the TRM  22.3.3 PSA Signature Register.

We have two CRC signature registers, high and low. I can provide you the example/code to pre calcuate CRC by 32-bit write, that is, write the CRC signature high and low register seperately.

I am not very clear about whether a 64-bit write works. Do both DMA and CPU 64-bit write work? I will check and give you feedback in a few days. 

Regards,

Haixiao

Hi,

Thank you for splitting the thread. Actually I am not well versed with community pages. I could not conclude how to create new thread?

Actually I am trying to use this CRC algorithm/function as an API. Can I use it like that? I am trying to pass the data to structure "crcModConfig_t" in the field "src_data_pat". Then I can calculate CRC of that using PSA registers.

Let me know if I can do that.

Regards,

Chitra

Click the "New Post" button to post something new:

I will give you an example to calculate the CRC using hardware and software.

Haixiao

Hi,

Thank you for an example. I shall work on this in a day's time and get back to you.

Can I use these function for application CRC or some other data CRC? I read a post which states that CRC module can be used only for calculating CPU/FPU register CRC.

Thank you for your support

Regards,

Chitra

Yes, what is CRC doing:

The master (CPU or DMA) write some data (dont care where it comes from) to the CRC signature register. Then the CRC module generate the CRC signature based on the data written and the initial signature value.

The previous post is done in compiler 5.1.1A, which is not published yet.
Here I transfer it into compiler version 4.9.6.8030.CRC_Example.zip

Regards,

Haixiao

Hi,

Logically it is correct but since I had read som post about CRC I just thought of confirming.

Thank you for example wiht correct compiler. I will work on it today.

For some reason i dont see New Post button on the my page. might be some firewall issue.

Regards,

Chitra

Hi,

I have few questions related to the example as my development board got damaged and i am unable to debug my application.

1) Why do we need CRC using DMA because I am using FULL CPU Mode for the computation? Is it mandatory?

2) Why do I need SCI_Init function becasue it works fine without this function call as well

3) What I understand from the example is in case hardware and software crc matches then we can conclude that CRC matches right? I am asking you this becasue I did not find the comparison in the example or is there any other way of comparing and concluding

4) In the main function from file sys_main.c, do I need to calculate CRC using both 32 (CRCSignLo_hard_32)and 64 (CRCSignLo_hard_64)bits and then compare the results? or if my data is 32 bit Ican use only 32 bit CRC functions and leave rest of them say use ""SoftCrcCal_32" and don't use "SoftCrcCal_64".

5) In case my data is 32 bit and I am using FULL CPU MODE, I can end my main function after calling "SoftCrcCal_32" in the sys_main.c file

Regards

Chitra

Chitra Sapre said:

Hi,

I have few questions related to the example as my development board got damaged and i am unable to debug my application.

1) Why do we need CRC using DMA because I am using FULL CPU Mode for the computation? Is it mandatory?

HW: This is a generic example showing the capabilities of the device. Choose CPU or DMA, whatever you like.

2) Why do I need SCI_Init function becasue it works fine without this function call as well

HW: As an example, I output the calculated CRC to the Hyperterminal so that I knew whether the result is correct or wrong. You don't need that in your application.

3) What I understand from the example is in case hardware and software crc matches then we can conclude that CRC matches right? I am asking you this becasue I did not find the comparison in the example or is there any other way of comparing and concluding

HW: I output them to the hyperterminal and compare them there. In your application, for the software crc (golden value), you can calculate with you PC or use MCU, and then compare the hardware CRC against this golden value. In the auto mode, you can save the golden value into one CRC registers and the CRC module will trigger an interrupt once the hardware CRC does not match the golden value.

4) In the main function from file sys_main.c, do I need to calculate CRC using both 32 (CRCSignLo_hard_32)and 64 (CRCSignLo_hard_64)bits and then compare the results? or if my data is 32 bit Ican use only 32 bit CRC functions and leave rest of them say use ""SoftCrcCal_32" and don't use "SoftCrcCal_64".

HW: No. You only need to calculate one of them. I show you all the calculation because I want to remind you that, 32 bit access and 64 bit access generate different CRC value.

5) In case my data is 32 bit and I am using FULL CPU MODE, I can end my main function after calling "SoftCrcCal_32" in the sys_main.c file

HW: SoftCrcCal_32 show you how to calculate the CRC using software, for example, you can port this function to visual C++ and calculate there. With our device, it can is calculated by the hardware CRC module (saves a lot of CPU load).

Regards

Chitra

Hi,

Thank you for clarification. My CRC is working fine now.

I am unable to debug since my assemly routine is throwing error. Error is some where in Halcogen generated asm functions. Error is very simple "Cannot redefine existing opcode 'AND' with .define" but I am unable to locate it. Any suggestions?

Code is pasted for the reference:

-------------------------------------------------------------------------------------------------------------------------

    .text
    .arm

 .cdecls C,NOLIST
 %{
    #include "ARM/CSA_Defs.inc"
    #include "BT_Startup.h"
 %}
 .include "BT_C_Structure_Offsets.inc"
    .page

;-------------------------------------------------------------------------------
; Initialize CPU Registers

    .def     _coreInitRegisters_
    .asmfunc

_coreInitRegisters_

        mov   r0,         lr
        mov   r1,         #0x03D0
        mov   r2,         #0x0000
        mov   r3,         #0x0000
        mov   r4,         #0x0000
        mov   r5,         #0x0000
        mov   r6,         #0x0000
        mov   r7,         #0x0000
        mov   r8,         #0x0000
        mov   r9,         #0x0000
        mov   r10,        #0x0000
        mov   r11,        #0x0000
        mov   r12,        #0x0000
        orr   r13,        r1,     #0x0001
        msr   cpsr_cxsf,  r13
        msr   spsr_cxsf,  r13
        mov   lr,         r0
        mov   r8,         #0x0000
        mov   r9,         #0x0000
        mov   r10,        #0x0000
        mov   r11,        #0x0000
        mov   r12,        #0x0000
        orr   r13,        r1,     #0x0002
        msr   cpsr_c,     r13
        msr   spsr_cxsf,  r13
        mov   lr,         r0
        orr   r13,        r1,     #0x0007
        msr   cpsr_c,     r13
        msr   spsr_cxsf,  r13
        mov   lr,         r0
        orr   r13,        r1,     #0x000B
        msr   cpsr_c,     r13
        msr   spsr_cxsf,  r13
        mov   lr,         r0
        orr   r13,        r1,     #0x0003
        msr   cpsr_c,     r13
        msr   spsr_cxsf,  r13

        fmdrr d0,         r1,     r1
        fmdrr d1,         r1,     r1
        fmdrr d2,         r1,     r1
        fmdrr d3,         r1,     r1
        fmdrr d4,         r1,     r1
        fmdrr d5,         r1,     r1
        fmdrr d6,         r1,     r1
        fmdrr d7,         r1,     r1
        fmdrr d8,         r1,     r1
        fmdrr d9,         r1,     r1
        fmdrr d10,        r1,     r1
        fmdrr d11,        r1,     r1
        fmdrr d12,        r1,     r1
        fmdrr d13,        r1,     r1
        fmdrr d14,        r1,     r1
        fmdrr d15,        r1,     r1
        bl    next1
next1
        bl    next2
next2
        bl    next3
next3
        bl    next4
next4
        bx    r0

    .endasmfunc

;-------------------------------------------------------------------------------
    .def     _coreEnableVfp_
    .asmfunc

_coreEnableVfp_

        mrc   p15,     #0x00,      r0,       c1, c0, #0x02
        orr   r0,      r0,         #0xF00000
        mcr   p15,     #0x00,      r0,       c1, c0, #0x02
        mov   r0,      #0x40000000
        fmxr  fpexc,   r0
        bx    lr

    .endasmfunc

;_coreEnableVfp_
;
 ;       mrc   p15,     #0x00,      r0,       c1, c0, #0x02
  ;      orr   r0,      r0,         #0xF00000
   ;     mcr   p15,     #0x00,      r0,       c1, c0, #0x02
    ;    mcr   p15,     #0x00,      r0,       c0, c0, #0x02
     ;   mov   r0,      #0x40000000
      ;  fmxr  fpexc,   r0
       ; bx    lr

   ; .endasmfunc

;-------------------------------------------------------------------------------
; Enable Offset via Vic controller

    .def     _coreEnableIrqVicOffset_
    .asmfunc

_coreEnableIrqVicOffset_

        mrc   p15, #0, r0,         c1, c0,  #0
        orr   r0,  r0,    #0x01000000
        mcr   p15, #0, r0,         c1, c0,  #0
        bx    lr

    .endasmfunc

;-------------------------------------------------------------------------------
; Enable core RAM ECC

    .def _coreEnableRamEcc_
    .asmfunc

_coreEnableRamEcc_

    ; Enabling reading writing to Secondary Auxiliary Registers

    MRC P15,    #0,     R1,     C9,     C12,    #0
    ORR R1,     R1,     #0x00000010
    MCR P15,    #0,     R1,     C9,     C12,    #0

    ; Enable parity checking DOTCM

    ORR R1,     R1,     #0x1 <<26
    DMB
    MCR P15,    #0,     R1,     C1,     C0,     #1
    ISB

    ; Enable parity checking D1TCM

    MRC P15,    #0,     R1,     C1,     C0,     #1
    ORR R1,     R1,     #0x1 <<27
    DMB
    MCR P15,    #0,     R1,     C1,     C0,     #1
    ISB

    ; Restore program counter

    MOV PC, LR

    .endasmfunc

;-------------------------------------------------------------------------------
; Disable core RAM ECC

    .def _CoreDisableRamEcc_
    .asmfunc

_CoreDisableRamEcc_

    ; Disable BOTCM RAM PARECCENRAM[1]

    MRC P15,    #0,     R1,     C1,     C0,     #1
    MVN R0,     #0x1 <<26
    AND R1,     R1,     R0
    MVN R0,     #0x1 <<27
    AND R1,     R1,     R0

    DMB
    MCR P15,    #0,     R1,     C1,     C0,     #1
    ISB

    ;disable B1TCM  PARECCENRAM[2]

    MRC P15,    #0,     R1,     C1,     C0,     #1
    DMB
    MCR P15,    #0,     R1,     C1,     C0,     #1
    ISB

    ;PMNC Register to pass ERROR

    MRC P15,    #0,     R1,     C9,     C12,    #0

    ;Clear 4th bit of PMNC Register

    MVN R0,     #0x00000010
    AND R1,     R1,     R0
    DMB
    MCR P15,    #0,     R1,     C9,     C12,    #0
    ISB

    ; Restore program counter

    MOV PC, LR

    .endasmfunc

--------------------------------------------------------------------------------------------------------------------------------

Also, when i try to access watchdog i am unable to access.

Any examples for stack configuration?

Regards,

Chitra

_coreInitStackPointer_ in sys_core.asm initialize the stack.

Can you publish the whole project? I can not compile it without the .h and .inc file you try to include in this asm.

Regards,

Haixiao

Hi

I can post the project. I am working for safety critical application. I will try to resolve the error for one more day.

Regards

Chitra

hi,

Sorry for the late reply. I was on vacation. My CRC algorithm is working fine now.

do yo have any file for assembly instructions? I want to have a look at the assembly instruction set. I will have to write some code for watchdog and other discrete which might need assembly coding. Also is there any example for GPIO mapping to discrete signals?

Thanks

Chitra