What should be the value for Single Bit Error Position while reading OTP Address 0xF008E3F0 for Bank7 ECC Check?

Pashan,

We are looking into this an will get back to you.

Hercules forum support

Hi Pashan,

  Not too sure of your question. Maybe you can elaborate a bit more. It seems that you are asking about the "error position" when reading from a TI OTP sector of the EEPROM bank (aka Bank7). What type of error (correctable or non-correctable) depends on what value is stored at the specified address and its coresponding ECC checksum. If it is a single bit error then the error bit position can be any one of the 64 bit data or even among one of the 8 ECC bits.

regards,

Charles

Hello Charles,

Yes, I am trying to verify FLEE Bank 7 OTP based ECC checking algorithm.

http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/135164/486982.aspx#486982

In the above link, John Hall mentioned that

For testing ECC errors on the EEPROM Emulation Bank or Customer OTP, we have pre-programmed single bit and double bit errors in OTP.

Single Bit:  (uint64 *) (0xF008E3F0)

Double Bit:  (uint64 *) (0xF008E3F8)

In the following link : http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/150568.aspx

He showed how the DATA is laid out.

This is data is for Bank 7 only.
ECC for both locations is for data = 0x123456789ABCDEF0

Reads of locations 0xF008E3F0-0xF008E3F7 give single bit error
Reads of locations 0xF008E3F8-0xF008E3FF give a double bit error

So, my question is that for the above information, you will see that only the last BIT is changed for Single Bit Error.

Hence,  EE_COR_ERR_POS Register at offset 0x318 of Flash Wrapper, I should see ZERO.
But I am seeing 0x20 as the value once I read Addess 0xF008E3F0.
I do get Single Bit Error status in EE_STATUS as well as in ESM.

Confusion is about EE_COR_ERR_POS value.
Please help,
Let me know if my question is still not clear.

Thank you.
Regards
Pashan

Hello Pashan,

  Can you tell me if you are reading 0xC856 or something else at the corresponding ECC location for these two 64-bit data? You can read the corresponding Bank7 TI OTP ECC at 0xF00C1C7E.

regards,

Charles

Hello Charles,

I am assuming I don't have to SETUP any Register in Flash Wrapper before reading the ECC Area of OTP related to Bank 7.

So, if I just read using LDRB Instruction from  0xF00C1C7E then  I get 0xB4.

For 0xF00C1C7F   I get 0x2A using LDRB Instruction.

Thank you.
Regards
Pashan

Hello Charles,

Attached are the Debugger Screen for easier understanding.

Thank you.
Regards
Pashan

Hello Pashan,

  I did some simple test. I enable ECC checking for the Bus2 i/F. I enable the profiling mode and set the threshold to 5. I read from 0xF008E3F0 5 time and I was able to see the correctable error counter increments for 5 times and then reset to zero. During this time the error position counter remains at 0. Can you please give me your exact setup? Also a screenshot of all the register values from flash wrapper staring at offset 0x300-0x320 will be helpful. I did the test on TMS570LS31x.

regards,

Charles

Hello Charles,

Can you please attach the complete DEMO you used to test.

I can tweak it to run on my setup.

Haixiao recently attached his Complete Project in the e2e : http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/281553.aspx

Please attach the complete project and from there I can compare easily with my Register Settings.
Make sure all the HEADER files are also there including C source files and Linker File as well as anything else so that I can also rebuild your project.
Also attach your MAP file and OUT files and so on.

Let me know if that is not possible.

Thank you.
Regards
Pashan

Hi Pashan,

  Please find attached the project. Put a breakpoint at line 53 and open the memory browser to view the flash FEE registers starting from 0xFFF87300. As you sequence through the loop to read the address 0xF008E3F0 you will see the error counter getting incremented until the threshold is reached upon which the error counter will reset to zero. When threshold is reach the FEE Profiling Error Flag, bit0 of EE_STATUS will set. The ESM GP1 channel 35 is also set. When reading the address 0xF008E3F8 the bit8 of EE_STATUS will get set to indicate a multibit error and ESM GP1 channel 36 is set.

2235.Bank7_OTP_ECC.zip

Hello Charles,

I have modified your sys_main.c [attached in the mail] and you will see the error occuring as mentioned below w.r.t. ERR_POS as 0x20.

Let me know if you can't see the fault.

Thank you.
Regards
Pashan

Hello Pashan,

  I could reproduce your observation. Bit9 (Error on Zero Fail Enable) of EE_CTRL1 makes a difference. I will investigate it and get back.

regards,

Charles